A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.     

A 5-GHz direct-conversion CMOS transceiver

A CMOS transceiver fully compliant with IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz) achieves a receiver sensitivity of -5 dBm for 64-QAM (quadrature amplitude modulation) with an error vector magnitude (EVM) of -29.3 dB. A single-sideband mixing technique for local-oscillator signal generation avoids frequency pulling. Realized in 0.18-/spl mu/m CMOS and operating from 1.8-V power supply, the design consumes 171 mW in receive mode and 135 mW in transmit mode while occupying less than 13 mm/sup 2/.     

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.     

A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter

A fully integrated dual-band transceiver is implemented in 0.18-/spl mu/m CMOS and is compliant with the IEEE 802.11a/b/g standards. The direct-conversion transceiver occupies 12 mm/sup 2/ in a QFN-40 package. A fractional-N synthesizer operates at twice the channel frequency, covering continuously bands from 4.9 to 5.9 GHz, as well as the 2.4-GHz band. The 5- and 2.4-GHz receivers achieve a sensitivity level below -73 dBm in the 54-Mb/s mode and below -93 dBm in the 6-Mb/s mode, while consuming 230 mW. A fast RSSI-channel power-detection system allows to power-down signal processing in the listen mode. The 5- and 2.4-GHz transmitters implement a wideband Cartesian feedback loop for enhanced EVM performances and improved spectrum masks compliance. The transmitters deliver -2-dBm average power with an EVM of 3% in the 54-Mb/s mode while consuming 300 mW.     

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.     

A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs

This paper describes a radio-frequency receiver targeting spread-spectrum wireless local-area-network applications in the 2.4-GHz band. Based on a direct-conversion architecture, the receiver employs partial channel selection filtering, dc offset removal, and baseband amplification. Fabricated in a 0.6-μm CMOS technology, the receiver achieves a noise figure of 8.3 dB, IP₃ of -9 dBm, IP₂ of +22 dBm, and voltage gain of 34 dB while dissipating 80 mW from a 3-V supply     

A CMOS frequency synthesizer with an injection-locked frequencydivider for a 5-GHz wireless LAN receiver

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 μm CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc     

A 5-GHz low-voltage and low-power CMOS LC voltage controlled oscillator for 802.11a wireless LAN applications

In this paper, a low phase noise and low power 5.15?GHz LC-tank VCO is presented and analysed. The phase noise achieved is??91,??116 and??126?dBc/Hz at 100?KHz, 1?MHz and 3?MHz offsets respectively from the carrier frequency of 5.15?GHz, with 1.8?V power supply voltage and giving a very low power consumption of about 2.5?mW by considering the proposed oscillator topology, which consumes less power than the classical oscillator using the traditional differential transconductor pair. A broad tuning range has been achieved by means of standard mode PMOS varactors. The tunability of the designed VCO covers 530?MHz, from 4.78?GHz up to 5.31?GHz. Predicted performance has been verified by analyses and simulations using ELDO-RF tool with 0.35?µm CMOS TSMC parameters.     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.     

A 2.4-GHz 0.25-/spl mu/m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A dual-mode transceiver integrates the transmitter of 0-dBm output power and the receiver for both Bluetooth with -87 dBm sensitivity and 802.11b with -86 dBm sensitivity in a single chip. A direct-conversion architecture enables the maximum reuse and the optimal current consumption of the various building blocks in each mode for a low-cost and low-power solution. A single-ended power-amplifer (PA) driver transmits the nominal output power of 0 dBm with 18-dB gain control in 3-dB steps. Only little area overhead is required in the baseband active filter and programmable gain amplifier (PGA) to provide the dual-mode capability with optimized current consumption. The DC-offset cancellation scheme coupled with PGAs implements the very low high-pass cutoff frequency with a smaller area than required by a simple coupling capacitor. Fabricated in 0.25-/spl mu/m CMOS process, the die area is 8.4 mm/sup 2/ including pads, and current consumption in RX is 50 mA for Bluetooth and 65 mA for 802.11b from a 2.7-V supply.     

可用于无线局域网802.11a标准的5-GHz CMOS功率放大器设计

介绍了TSMC0．18μm CMOS工艺的功率放大器的设计,给出了仿真结果,版图照片和芯片键合测试方案。该电路采用三级差分放大结构,在其工作频段内满足绝对稳定条件,在3．3V电源电压下,增益为27．3dB,输入1dB压缩点为-7dBm,最大输出功率为19．3dBm,输入端反射系数S11=-30dB,可用于无线局域网802．11a标准的系统中。     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.     

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

Packet telephony support for the IEEE 802.11 wireless LAN

Packet telephony is one of the most promising applications in the Internet. In this paper, we propose a modified MAC protocol supporting voice traffic over the IEEE 802.11 WLAN. The proposed scheme adapts the power-saved mode of the IEEE 802.11 specifications in such a way that it approaches the TDM access mode carrying voice traffic, and is compatible with the IEEE 802.11 standard. Simulation results show that the proposed scheme does not degrade the performance of the IEEE 802.11 WLAN using the DCF and also provides good voice quality     

A survey of QoS enhancements for IEEE 802.11 wireless LAN

Quality‐of‐service (QoS) is a key problem of today's IP networks. Many frameworks (IntServ, DiffServ, MPLS etc.) have been proposed to provide service differentiation in the Internet. At the same time, the Internet is becoming more and more heterogeneous due to the recent explosion of wireless networks. In wireless environments, bandwidth is scarce and channel conditions are time‐varying and sometimes highly lossy. Many previous research works show that what works well in a wired network cannot be directly applied in the wireless environment. Although IEEE 802.11 wireless LAN (WLAN) is the most widely used IEEE 802.11 wireless LAN (WLAN) standard today, it cannot provide QoS support for the increasing number of multimedia applications. Thus, a large number of 802.11 QoS enhancement schemes have been proposed, each one focusing on a particular mode. This paper summarizes all these schemes and presents a survey of current research activities. First, we analyze the QoS limitations of IEEE 802.11 wireless MAC layers. Then, different QoS enhancement techniques proposed for 802.11 WLAN are described and classified along with their advantages/drawbacks. Finally, the upcoming IEEE 802.11e QoS enhancement standard is introduced and studied in detail. Copyright © 2004 John Wiley & Sons, Ltd.     

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-/spl mu/m CMOS

This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.