AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

SOI 动态阈值MOS 研究进展

随着器件尺寸的不断缩小,传统MOS器件遇到工作电压和阈值电压难以等比例缩小的难题,以至于降低电路性能,而工作在低压低功耗领域的SOI DTMOS可以有效地解决这个问题。本文介绍了四种类型的SOI DTMOS器件．其中着重论述了栅体直接连接DTMOS、双栅DTMOS和栅体肖特基接触DTMOS的工作原理和性能．具体分析了优化器件性能的五种方案,探讨了SOI DTMOS存在的优势和不足。最后指出,具有出色性能的SOI DTMOS必将在未来的移动通讯和SOC等低压低功耗电路中占有一席之地。     

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications

Schottky barrier MOSFETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-65-nm technology nodes. An asymmetric Schottky tunneling source SOI MOSFET (STS-FET) is proposed in this paper. The Schottky tunneling source SOI MOSFET has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the concept of a gate-controlled Schottky barrier tunneling at the source. The device was optimized with respect to various parameters such as Schottky barrier height and gate oxide thickness. The optimized device shows excellent short channel immunity, compared to conventional SOI MOSFETs. The asymmetric nature of the device has been shown to improve the leakage current as well as the linear characteristics of the device as compared to conventional Schottky FETs. The STS-FET was fabricated, using conventional processes combined with the present NiSi technology and large angle implantation, and successfully demonstrated. The high immunity to short channel effects improves the scalability, and the output resistance of the device also makes it an attractive candidate for mixed-mode applications.      

Comparison of the scaling characteristics of nanoscale SOI N-channel multiple-gate MOSFETs

As MOSFET scaling pushes channel lengths below 65 nm, device designs utilizing fully depleted silicon-on-insulator (SOI) technology and employing two or more gates are becoming increasingly attractive as a means to counteract short channel effects. The presence of multiple gates enhances the total control that the gate exercises on the channel region and the SOI technology allows for a significant reduction in the junction capacitance. In combination, these two factors result in devices that exhibit superior characteristics to the conventional planar MOSFET. This paper compares the variation in the switching performance of the three leading multi-gate MOSFET designs, namely the FinFET, TriGate, and Omega-gate. A 3-dimensional, commercial numerical device simulator is employed to investigate the device characteristics using a common set of material parameters, device physics models, and performance metrics. Examined initially are the short-channel effects including the subthreshold slope (S) and the drain-induced barrier lowering as the gate length is scaled down to 20 nm. Subsequently investigated and compared are the effects of scaling of the fin’s body width and height, the oxide thickness, and channel doping. The investigation reveals that the Omega-gate MOSFET shows the best scaling characteristics at a particular device dimension with the TriGate device showing the least variation in characteristics as device dimensions vary.     

A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

For the first time, a novel device concept of a quasi-silicon-on-insulator (SOI) MOSFET is proposed to eliminate the potential weaknesses of ultrathin body (UTB) SOI MOSFET for CMOS scaling toward the 35-nm gate length, and beyond. A scheme for fabrication of a quasi-SOI MOSFET is presented. The key characteristics of quasi-SOI are investigated by an extensive simulation study comparing them with UTB SOI MOSFET. The short-channel effects can be effectively suppressed by the insulator surrounding the source/drain regions, and the suppression capability can be even better than the UTB SOI MOSFET, due to the reduction of the electric flux in the buried layer. The self-heating effect, speed performance, and electronic characteristics of quasi-SOI MOSFET with the physical channel length of 35 nm are comprehensively studied. When compared to the UTB SOI MOSFET, the proposed device structure has better scaling capability. Finally, the design guideline and the optimal regions of quasi-SOI MOSFET are discussed.     

High-current small-parasitic-capacitance MOSFET on a poly-Siinterlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO₂. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO₂/poly-Si/500-nm SiO₂) wafer. In this device, the highly concentrated p⁺ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages     

A novel nanoscale SOI MOSFET with Si embedded layer as an effective heat sink

A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications.     

Diamond layout style impact on SOI MOSFET in high temperature environment

This work performs an experimental comparative study between the Diamond (hexagonal gate geometry) and Standard layouts styles for Metal–Oxide–Semiconductor Field Effect Transistor in high temperatures environment. The devices were manufactured with the 1 μm Silicon-on-Insulator CMOS technology. The results demonstrate that the Diamond SOI MOSFET is capable to keep active the Longitudinal Corner Effect and the Parallel Association of MOSFET with Different Channel Lengths Effect in high temperature conditions and consequently to continue presenting a better electrical performance than the one found in the conventional SOI MOSFET.     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

Elimination of kink effect in fully depleted complementaryburied-channel SOL MOSFET (FD CBCMOS) based on silicon direct bondingtechnology

For the fully depleted complementary buried-channel MOSFET (FD CBCMOS) discussed, although its operational principle is similar, its structure is different from that of the conventional buried-channel MOSFET in which a p-n junction exists at the surface of the channel region. Moreover, the p-n junction is totally eliminated in the device structure for both source and drain. Low interface charges in the silicon-on-insulator/silicon direct bonding (SOI/SDB) structure allow the fabrication of the FD CBCMOS. Numerical simulation and experimental measurement have demonstrated that no kink effect is present and that the device has the potential for VLSI applications due to the absence of the p-n junction and the superior SOI/SDB material quality     

Performance comparison of channel engineered deep sub-micrometer pseudo SOI n-MOSFETs

In this paper, with the help of extensive TCAD simulations, a novel channel and source/drain (S/D) impurity profile engineering has been proposed for pseudo SOI MOSFET structures in order to reduce their junction capacitances. It has been shown that this approach leads to improved performance and lower power dissipation for sub 100 nm CMOS technologies. These pseudo SOI structures studied in this work are referred to as the Source Drain On Depletion Layer (SDODEL) MOSFETs in the earlier studies. We have investigated DC characteristics and analog performance parameters in Single Halo SDODEL MOSFET, Double Halo SDODEL MOSFET and compared their performance with Double Halo MOSFETs (which will henceforth be referred to as Control MOSFETs) with extensive process and device simulations. Our results shows that, in Single Halo SDODEL MOSFET there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g_m/I_D etc.) for the sub 100 nm technologies.     

Proposal of preliminary device model and scaling scheme of cross-current tetrode SOI MOSFET aiming at low-energy circuit applications

This paper describes a preliminary attempt with a semi-analytical model and a scaling scheme of the cross-current tetrode (XCT) silicon-on-insulator (SOI) MOSFET aiming at low energy-dissipation circuit applications. The channel-current model for XCT MOSFET is separated into an intrinsic MOSFET part and a parasitic junction-gate field-effect transistor (JFET) part. Models for MOSFET and JFET are proposed by taking the potential coupling between MOSFET and JFET. The later part of the paper introduces experiments on the original SOI nMOSFET and XCT nMOSFET. This paper stresses the fundamental operations and features of the XCT device structure. Calculation results of I-V characteristics from the semi-analytical model are compared with the measurement values. It is shown that the proposed model reproduces the measured values successfully. In addition, design guidelines for XCT devices and scaling issues are discussed from the viewpoint of performance control aiming at low energy-dissipation circuit applications. Finally, preliminary circuit simulation results of XCT CMOS devices are revealed to demonstrate the definite low-energy performance.     

Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET

This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20-nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.     

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 μm have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact     

薄膜全耗尽应变Si SOI MOSFET特性模拟与优化分析

研究了应变Si沟道引入对薄膜全耗尽SOI MOSHET器件特性的影响,并分析了器件特性改进的物理机理.与传统的SOI MOSFET结构相比,器件的驱动电流和峰值跨导都有明显提高,对n-FET分别为21%和16.3%,对p-FET为14.3%和10%.应变si沟道的引入还降低了器件的阈值电压,这有益于集成电路中供电电压的降低和电路功耗的减小.另外,本文还对新结构中的Ge含量进行了优化分析,认为当Ge含量为30%时,器件有较好的电特性,而且不会增加器件制作的工艺成本.     

Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's

The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO2) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.     

Study on the device characteristics of a quasi-SOI power MOSFETfabricated by reversed silicon wafer direct bonding

The device characteristics of a quasi-SOI power MOSFET were investigated to obtain its optimum device structure. The oxide at the original bottom surface of the bulk power MOSFET of the quasi-SOI power MOSFET formed by reversed silicon wafer direct bonding acts as the buried oxide of the conventional SOI power MOSFET. The short channel effect of the quasi-SOI power MOSFET was larger than that in the conventional SOI power MOSFET. It was suppressed by increasing the width of the oxide in the body region, and the parasitic bipolar effect was suppressed by decreasing it. We also propose a new device structure which can suppress the short channel effect and parasitic bipolar effect of a quasi-SOI power MOSFET based on the results of these experiments