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For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs. 相似文献
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SoC嵌入式flash存储器的内建自测试设计 总被引:1,自引:1,他引:0
深亚微米技术背景下,嵌入式存储器在片上系统芯片(system-on-a-chip,SoC)中占有越来越多的芯片面积.嵌入式存储器的测试正面临诸多新的挑战。本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。详细讨论了专用硬件方式内建自测试的设计及其实现,并且提出了一种新型的软硬协同方式的内建自测试设计。这种新型的测试方案目标在于结合专用硬件方式内建自测试方案并有效利用SoC芯片上现有的资源,以保证满足测试过程中的功耗限制,同时在测试时间和芯片面积占用及性能之间寻求平衡。最后对两种方案的优缺点进行了分析对比。 相似文献
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Patel K.N. Markov I.L. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(10):1076-1080
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on long, adjacent bus wires can lead to timing violations and logic faults. At the same time, system-level interconnects have also become more susceptible to other less predictable forms of interference such as noise induced by power grid fluctuations, electromagnetic interference, and alpha-particle radiation. Previous work has treated these systematic and nonsystematic forms of noise separately. We propose to make system-level interconnects more robust using encoding that simultaneously addresses error-correction requirements and crosstalk noise avoidance. This is more efficient than satisfying these requirements separately. We give algorithms for obtaining optimal encodings and present a practical class of codes called boundary-shift codes. We evaluate the overhead of our method, and make comparisons to using error-correction with simple shielding. 相似文献
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As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis. 相似文献
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The rising level of complexity and speed of SoC makes it increasingly vital to test adequately the system for signal integrity. Voltage overshoot is one of the integrity factors that has not been sufficiently addressed for the purpose of testing and reliability. Overshoots are known to inject hot-carriers into the gate oxide and cause permanent degradation of MOSFET transistors' performance. This performance degradation creates a serious reliability concern. Unfortunately, accurate parasitic extraction and simulation to detect the interconnect problems is very time consuming and very sensitive to the circuit characteristics and thus is not practical for large SoC. This paper presents a built-in chip methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. This built-in test strategy does not require external probing or signal waveform monitoring. Instead, the overshoot detector cells monitor signals received by a core (e.g. from the system bus) and record the occurrence of overshoots over a period of operation. The overshoot information accumulated by these cells can be compressed and scanned out efficiently And inexpensively for final quality grading, reliability analysis and diagnosis. 相似文献
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Shannon L. Chow P. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(4):377-390
As the complexity of designing system-on-chips increases, so does the need to abstract low-level design issues to improve designer productivity. The reuse of previously designed Intellectual Property (IP) modules is a common form of abstraction used to reduce design time. However, different applications typically use a variety of physical interfaces, communication protocols, and global system-level control for IP modules, which complicates design reuse. In this paper, we describe the SIMPPL system model and an abstraction for IP modules, called the computing element (CE), that facilitate the SoC design for both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The CE abstraction decouples the datapath and system-level communication from the application-specific control to promote design reuse by localizing control redesign of IP for new applications. The SIMPPL model facilitates multi-clock domain SoC designs and expedites system integration by defining the intermodule links and communication protocols 相似文献
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With technology scaling, the number of sensors integrated into modern system-on-chip (SoC) designs has increased greatly over the past several years. These sensors must be accessed for a number of reasons (test, configuration, calibration, etc.). This paper proposes a novel sensor access mechanism (SAM) to address sensor access in various operation modes, including manufacturing test mode, functional mode, built-in self-test (BIST) mode, silicon validation mode, and calibration mode. Within this mechanism, we develop a structured and scalable sensor access architecture and a pipeline sensor access flow. The SAM architecture addresses sensor insertion and access in different scenarios, while the pipeline flow is developed by utilizing the features of sensor measurement and hardware architecture to improve the efficiency of sensor access. Moreover, SAM standardizes the testing and measurement of embedded sensors by providing easy and effective access to sensors distributed across the SoC. Further, SAM is JTAG-compatible and practice-oriented for easy industry adoption. Various simulation results, collected by integrating SAM into several benchmarks, demonstrate that sensor controllability and observability can be achieved with high efficiency and low overhead using the proposed architecture. 相似文献
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SoC芯片内对于混合信号电路测试有着举足轻重的作用.本文介绍了一种通过谱密度分析方法的混合电路内建自测试.此方法通过使用噪声源与比较器数字量化得到被测信号的频谱特性.它的主要特点是电路简单、抗干扰性能强和多点插入多路并行采集,不需要多位AD转换器和多路选择开关.此方法基本上是全数字式的,采用一位量化,数据处理速度快,能满足给定条件下的实时处理要求;并可利用系统内已有的资源,适应于SoC环境.本文给出了系统实现的详细结构和一个测试锁相环电路的测试仿真实例,验证了谱分析方法的测试有效性. 相似文献
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文章提出了一种简单有效的双矢量测试BIST。实现方案.其硬件主要由反馈网络可编程且种子可重置的LF—SR和映射逻辑两部分构成。给出了一种全新的LPSR最优种子及其反馈多项式组合求取算法,该算法具有计算简单且容易实现的特点。最后。使用这种BIST、方案实现了SoC中互联总线间串扰故障的激励检测,证明了该方案在计算量和硬件开销方面的优越性。 相似文献
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An architecture for system-level self-test of a wireless communication transceiver integrates the functional (parametric) self-test of the radio frequency subsystem, and the structural self-test of the digital subsystem. The digital subsystem is tested using extensions of the IEEE 1149.1 boundary scan standard to verify connections within circuit boards and between boards. The RF subsystem is tested using a loopback connection between the RF transmitter and receiver. An RF parametric self-test is performed using a digitally modulated signal (as opposed to a sinusoidal tone) as the test stimulus, and using samples from the receiver digitizer as test data. This loopback test scheme imposes a relatively small overhead on the RF system design 相似文献
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Dimitris Gizopoulos 《Microelectronics Journal》2004,35(5):443-449
On-line testing for complex system-on-chip architectures requires a synergy of concurrent and non-concurrent fault detection mechanisms. While concurrent fault detection is mainly achieved by hardware or software redundancy, like duplication, non-concurrent fault detection, particularly useful for periodic testing, is usually achieved through hardware-based self-test.Software-based self-test has been recently proposed as an effective alternative to hardware-based self-test allowing at-speed testing while eliminating area, performance and power consumption overheads.In this paper, we investigate the applicability of software-based self-test to non-concurrent on-line testing of embedded processor cores and define, for the first time, the corresponding requirements. Low-cost, in-field testing requirements, particularly small test execution time and low power consumption guide the development of self-test routines. We show how self-test programs with a limited number of memory references and based on compact test routines provide an efficient low-cost on-line test strategy for an RISC processor core. 相似文献
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Compact physical models are derived for the delay and crosstalk of on-chip coplanar transmission lines, which are used in state-of-the-art high-speed microprocessors. These lines are mainly used for long global interconnects that are relatively thick and wide and have prominent inductive effects. The models are then used to optimize the design of coplanar global interconnects. 相似文献
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The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead. 相似文献
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Voyiatzis I. Paschalis A. Gizopoulos D. Kranitis N. Halatsis C. 《Reliability, IEEE Transactions on》2005,54(1):69-78
Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation. 相似文献
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This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock. 相似文献
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Yi Zhao Dey S. Li Chen 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(7):746-755
With processors and system-on-chips using nano-meter technologies, several design and test efforts have been recently developed to eliminate and test for many emerging DSM noise effects. In this paper, we show the emergence of multisource noise effects, where multiple DSM noise sources combine to produce functional and timing errors even when each separate noise source itself does not. We show the dynamic nature of multisource noise, and the need for online testing to detect such noise errors. We propose an online approach based on low-cost double-sampling data checking circuit to test for such noise effects in on-chip buses. Based on the proposed circuit, an effective and efficient testing methodology has been developed to facilitate online testing for generic on-chip buses. The applicability of this methodology is demonstrated through embedding the online detection circuit in a bus design. The validated design shows the effectiveness of the proposed testing methodology for multisource noise-induced errors in global interconnects and buses. 相似文献
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To increase the number of test points, while still keeping low pint overhead, an alternative built-in self-test (BIST) structure using current copiers is presented. The BIST structure allows simultaneous sampling of either voltage or current test data at various test points and shifting the data for fault diagnosis and testing.<> 相似文献