89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region     

Effect of reduced temperature on the fT ofAlGaAs/GaAs heterojunction bipolar transistors

The high-frequency and DC performances of single-heterojunction Al _0.25Ga_0.75As/GaAs heterojunction bipolar transistors (HBTs) have been measured at temperatures between 300 and 110 K. It is found that the maximum unity-current-gain cutoff frequency increases from 26 GHz at 300 K to 34 GHz at 110 K. It is shown that electron diffusion as determined from the majority-carrier mobility does not accurately estimate the base transit time, at least until corrections for degeneracy and minority-carrier mobility enhancement are included. Reasonable agreement is obtained assuming that base transport is limited by the thermal velocity of electrons at reduced temperatures     

MBE-grown Si/SiGe HBTs with high β, fT,and fmax

Si/SiGe heterojunction bipolar transistors (HBTs) were fabricated by growing the complete layer structure with molecular beam epitaxy (MBE). The typical base doping of 2×10¹⁹ cm^-3 largely exceeded the emitter impurity level and led to sheet resistances of about 1 kΩ/□. The devices exhibited a 500-V Early voltage and a maximum room-temperature current gain of 550, rising to 13000 at 77 K. Devices built on buried-layer substrates had an f_max of 40 GHz. The transit frequency reached 42 GHz     

Improved current gain and fT through dopingprofile selection in linearly graded heterojunction bipolar transistors

Analytical and experimental results are used to show that extension of a thin p-doped layer of base doping into the graded-gap region, close to the base, of an n-p-n AlGaAs/GaAs heterojunction bipolar transistor and removing n-type dopant from the rest of the linearly graded AlGaAs region improves current gain β and unity gain cutoff frequency f_T. Current gain is significantly improved by reducing recombination near the metallurgical interface and using the effective electric field from the grading to accelerate electrons as they are injected into the p-base. The doping profile also inhibits the formation of a potential minimum in which electrons can be stored in close proximity to the base. This greatly improves f_T, and does not hamper the current injection or increase the turn-on voltage. Space-charge recombination current is also reduced, due to the carrier density reduction associated with the effective electric field due to the graded gap     

Importance of source and drain resistance to the maximum fT of millimeter-wave MODFETs

The usual approximate expression for measured f_T =[g_m/2π (C_gs+C _gd)] is inadequate. At low drain voltages just beyond the knee of the DC I-V curves, where intrinsic f _t is a maximum for millimeter-wave MODFETs, the high values of C_gd and G_ds combine with the high g_m to make terms involving the source and drain resistance significant. It is shown that these resistances can degrade the measured f_T of a 0.30-μm GaAs-AlGaAs MODFET from an intrinsic maximum f_T value of 73 GHz to a measured maximum value of 59 GHz. The correct extraction of maximum f_T is essential for determining electron velocity and optimizing low-noise performance     

1/f noise in n-p-n GaAs/AlGaAs heterojunction bipolartransistors:iImpact of intrinsic transistor and parasitic seriesresistances

1/f noise experiments were performed for n-p-n GaAs/AlGaAs HBTs as a function of forward bias at room temperature. The experimental data are discussed with the help of new expressions for the 1/f noise in bipolar transistors where the influence of internal parasitic series resistances has been taken into account. At low forward currents the 1/f noise is determined by spontaneous fluctuations in the base and collector currents. At fixed bias, the collector current noise exceeds the base current noise. At higher forward currents the parasitic series resistances and their 1/f noise become important. Experimental results from the literature are compared with the results     

Fabrication of 200-GHz fmax resonant-tunnelingdiodes for integration circuit and microwave applications

Room-temperature current densities of 1.3×10⁵ A/cm² and peak-to-valley ratios of 2.5 have been achieved for resonant tunneling diodes (RTDs) in the GaAs/AlAs material system. The devices were fabricated in a microwave-compatible process using topside contacts and a semi-insulating substrate to allow device integration. Proton implantation creates a nonconducting surface compatible with high-frequency coplanar transmission lines and other passive microwave structures     

Bias dependence of fT and fmax in anIn0.52Al0.48As/n+-In0.53Ga0.47As MISFET

Detailed microwave characterization of a recently fabricated In _0.52Al_0.48As/n⁺-In_0.53Ga _0.47As MISFET reveals that high values of current-gain cutoff frequency (f_T) and unilateral-gain cutoff frequency (f_max) are obtained for a broad range of gate bias voltage values. A significant peak in f_T and f _max has also been observed at high gate-source bias values. The peak coincides with the onset of electron accumulation at the heterointerface and is attributed to reduced ionized impurity scattering coupled with reduced drain conductance. This result suggests an improved device structure that optimizes operation in the accumulation regime     

Reconciliation of methods for estimating fmaxfor microwave heterojunction transistors

An attempt is made to reconcile the various approaches that have recently been used to estimate the maximum frequency of oscillation f_max in high-performance AlGaAs/GaAs HBTs. f_max is computed numerically from the full expression for Mason's invariant gain using y-parameters derived from the different approaches, i.e., the hybrid-π equivalent circuit, the T-equivalent circuit, and the drift-diffusion equations. It is shown that the results for f_max are essentially the same, irrespective of the source of the y-parameters, provided that the phase delays due to transit of carriers across the base and the collector-base depletion region are properly accounted for. It is also shown, for the particular device studied, that the widely used analytical expression for f_max, involving f _T and effective base resistance and collector capacitance, is remarkably accurate for frequencies below those at which transit-time effects become important     

Process and device characterization for a 30-GHz fT submicrometer double poly-Si bipolar technology using BF2-implanted base with rapid thermal process

Process and device parameters are characterized in detail for a 30-GHz f_T submicrometer double poly-Si bipolar technology using a BF₂-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050°C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7×10^-7 Ω-cm², while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors     

Reduction of ft by nonuniform base bandgapnarrowing

Analytical and simulation results are presented to illustrate qualitatively the effect of doping on base transit time. Nonuniform base bandgap narrowing (BGN) in silicon bipolar transistors can give rise to an electric field that is comparable to and against the built-in field. The base transit time τ is subsequently increased, leading to a deterioration of the cutoff frequency f₁. It is shown that the BGN effectively reduces the impurity profile grading factor K and subsequently the transit-time coefficient η. Physically, the minority carriers can be thought of as moving in a new profile characterized by a reduced η but in the absence of BGN. Unlike earlier investigations which also consider effective BGN dopings but ignore the field effects, this treatment includes their impact on the minority-carrier base transit time. For a steep exponential profile with strong BGN, an increase of η by a factor 3.57 at 300 K is calculated. Device simulations predict a smaller f_t reduction factor of 1.5 for more general profiles     

Hot-electron InGaAs/InP heterostructure bipolar transistors withfT of 110 GHz

A hot-electron InGaAs/InP heterostructure bipolar transistor (HBT) is discussed. A unity-current-gain cutoff frequency of 110 GHz and a maximum frequency of oscillation of 58 GHz are realized in transistors with 3.2×3.2-μm² emitter size. Nonequilibrium electron transport, with an average electron velocity approaching 4×10⁷ cm/s through the thin (650 Å) heavily doped (p=5×10¹⁹ cm^-3) InGaAs base and 3000-Å-wide collector space-charge region, results in a transit delay of 0.5 ps corresponding to an intrinsic cutoff frequency of 318 GHz     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

0.33-μm gate-length millimeter-wave InP-channel HEMTs with highf1 and fmax

The fabrication of 0.33-μm gate-length AlInAs/InP high electron mobility transistors (HEMTs) is reported. These InP-channel devices have f_t values as high as 76 GHz, f_max values of 146 GHz, and maximum stable gains of 16.8, 14, and 12 dB at 10, 18, and 30 GHz, respectively. The extrinsic DC transconductances are as high as 610 mS/mm; with drain-source breakdown voltages exceeding 10 V. The effective electron velocity in the InP channel is estimated to be at least 1.8×10⁷ cm/s, while the f_tL_g product is 29 GHz-μm. These results are comparable to the best reported results for similar InGaAs-channel devices     

On the leverage of high-fT transistors foradvanced high-speed bipolar circuits

A detailed study on the leverage of high-f_T transistors for advanced high-speed bipolar circuit applications is presented. It is shown that for the standard ECL (emitter-coupled logic) circuit, the leverage of high f_T is limited by the passive resistors (emitter-follower resistor and collector load resistor) and wire delay, especially in the low-power regime. For the standard NTL (nonthreshold logic) circuit, the leverage is higher due to its front-end configuration and lower power supply value. As the passive resistors are decoupled from the delay path in various advanced circuits utilizing active-pull-down schemes, the leverage of high F_T becomes more significant     

An input-free VT extractor circuit using atwo-transistor differential amplifier

A three-terminal circuit (power, ground, and output) that provides a DC output voltage equal to the MOS threshold voltage V_T is presented. The circuit uses the four-terminal extractor topology of Z. Wang (1992), but it adds self-biasing and a two-transistor differential amplifier to provide a ground-referenced output voltage     

1/f noise in GaAs filaments

A typical 1/f noise is excited in GaAs filament with the Hooge noise parameter of about α_H=2×10^-3 . The noise level increases in proportion to the square of the terminal voltage, and decreases approximately in inverse proportion to the total number of carriers within the device. A transition from the typical 1/f noise characteristics to the diffusion noise characteristics of MESFETs was observed when the electric field was increased above 1 kV/cm. The noise parameters were also investigated as a function of the device width between 2 and 200 μm. Deep levels within the n-GaAs active layer and the high electric field are the main factors of the nonideal 1/f characteristics     

Bulk and surface 1/f noise

The 1/f noise of an n-type silicon MOSFET has been studied under conditions ranging from accumulation to depletion at 300 K. The experimental results are interpreted in terms of a bulk phenomenon and are characterized by Hooge's empirical 1/f noise parameter α with values between 10^-7 and 10^-5. The α value for surface conduction at strong accumulation can be at least one order of magnitude larger than the value for bulk conduction     

On 1/f trapping noise in MOSTs

New calculations are given for the 1/f noise in metal-oxide-semiconductor transistors (MOSTs) based on the McWhorter model (number fluctuations). Particular attention is paid to two regions of the drain current-voltage characteristic: weak inversion and near saturation. The results are at variance with previous theories, where some errors have been made. The gravest error was the violation of the physical law whereby the variance of the number of carriers N in the channel is ⩽N. The calculations do not give a divergent noise power at current saturation, as found by other authors. In the ohmic region, the relation between the spectral density of the drain current fluctuations and the number of carriers is determined. The Langevin method and the Klaassen-Prins method for calculating the 1/f noise in MOSTs are discussed and shown to have been used incorrectly when the mobility and the Hooge 1/f noise parameter depend on position in the channel