1.5-/spl mu/m InGaAsP-InP slab-coupled optical waveguide lasers

We report the demonstration of high-power semiconductor slab-coupled optical waveguide lasers (SCOWLs) operating at a wavelength of 1.5 /spl mu/m. The lasers operate with large (4/spl times/8 /spl mu/m diameter) fundamental mode and produce output power in excess of 800 mW. These structures have very low loss (/spl sim/0.5 cm/sup -1/) enabling centimeter-long devices for efficient heat removal. The large fundamental mode allows 55% butt-coupling efficiency to standard optical fiber (SMF-28). Comparisons are made between SCOWL structures having nominal 4- and 5-/spl mu/m-thick waveguides.     

Evanescently coupled photodiodes integrating a double-stage taper for 40-Gb/s applications-compared performance with side-illuminated photodiodes

The design, fabrication, and performance of double-stage taper photodiodes (DSTPs) are reported. The objective of this work is to develop devices compatible with 40-Gb/s applications. Such devices require high efficiency, ultrawide band, high optical power handling capability, and compatibility with low-cost module fabrication. The integration of mode size converters improves both the coupling efficiency and the responsivity with a large fiber mode diameter. Responsivity of 0.6 A/W and 0.45 A/W are achieved with a 6-/spl mu/m fiber mode diameter and cleaved fiber, respectively, providing relaxed alignment tolerances (/spl plusmn/1.6 /spl mu/m and /spl plusmn/2 /spl mu/m, respectively), compatible with cost-effective packaging techniques. DSTPs also offer a wide bandwidth greater than 40 GHz and transverse-electric/transverse-magnetic polarization dependence lower than 0.2 dB. Furthermore, a DSTP saturation current as high as 11 mA results in optical power handling greater than +10 dBm and a high output voltage of 0.8 V. These capabilities allow the photodiode to drive the decision circuit without the need of a broad-band electrical amplifier. The DSTP devices presented here demonstrate higher responsivities with large fiber mode diameter and better optical power handling capabilities and are compared with classical side-illuminated photodiodes.     

A 0.25-/spl mu/m 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer

A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-/spl mu/m 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as a diode linearizer. It is believed that this is the first reported use of the diode linearization technique in CMOS PA design. It shows effective improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using an FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potential for medium power RF amplification at 2.4 GHz wireless communication band.     

Pr/sup 3+/-doped fluoride fiber amplifier module pumped by a fiber coupled master oscillator/power amplifier laser diode

We constructed the first Pr/sup 3+/-doped fluoride fiber amplifier (PDFA) module pumped by a fiber-coupled master oscillator/power amplifier laser diode (MOPA-LD) operating at 1.017 /spl mu/m. The maximum signal gain and noise figure were 30.5 and 5.5 dB, respectively. An output power of 18 dBm was achieved at an input signal power of 0 dBm. Furthermore, we showed that the use of MOPA-LD pumping, rather than conventional Nd-YLF laser pumping, makes it possible to halve the length of the Pr/sup 3+/-doped fluoride required in the amplifier module and also allows a broader spectral bandwidth to be achieved.     

A fully integrated 5.3-GHz 2.4-V 0.3-W SiGe bipolar power amplifier with 50-/spl Omega/ output

A radio frequency power amplifier for 4.8-5.7 GHz has been realized in a 0.35-/spl mu/m SiGe bipolar technology. The balanced two-stage push-pull power amplifier uses two on-chip transformers as input-balun and for interstage matching. Further, it uses three coils for the integrated LC-output balun and the RF choke. Thus, the power amplifier does not require any external components. At 1.0-V, 1.5-V, and 2.4-V supply voltages, output powers of 17.7 dBm, 21.6 dBm, and 25 dBm are achieved at 5.3 GHz. The respective power-added efficiencies (PAE) are 15%, 22%, and 24%. The small-signal gain is 26 dB. The output 1-dB compression point at 2.4 V is 22 dBm with a PAE of 14%.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

1.55 mu m polarization-insensitive high-gain tensile-strained-barrier MQW optical amplifier

A polarization-insensitive semiconductor optical amplifier was realized at a wavelength of 1.55 mu m. The active layer consisted of a tensile-strained-barrier multiple quantum well (MQW) structure. At a driving current of 150 mA, no dependence of the saturation characteristics on modes was obtained. The saturation output power at which the gain decreases 3 dB is 13.3 dBm. A slightly higher saturation output power of 14 dBm was measured at a driving current of 200 mA. No large difference was observed between transverse-electric (TE) and transverse-magnetic (TM) modes. A high gain of 27.5 dB at a polarization sensitivity of 0.5 dB and a high saturation output of 14 dBm were realized simultaneously by using a longer device with reduced residual facet reflectivities.<>     

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

A polar modulator transmitter for GSM/EDGE

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.     

1.58-/spl mu/m broad-band erbium-doped tellurite fiber amplifier

This paper describes the development of a 1.58-/spl mu/m broad-band and gain-flattened erbium-doped tellurite fiber amplifier (EDTFA). First, we compare the spectroscopic properties of various glasses including the stimulated emission cross sections of the Er/sup 3+4/ I/sub 13/2/ /sup 4/I/sub 15/2/ transition and the signal excited-state absorption (ESA) cross sections of the Er/sup 3+4/ I/sub 13/2/ - /sup 4/I/sub 9/2/ transition. We detail the amplification characteristics of a 1.58-/spl mu/m-band EDTFA designed for wavelength-division-multiplexing applications by comparing it with a 1.58-/spl mu/m-band erbium-doped silica fiber amplifier. Furthermore, we describe the 1.58-/spl mu/m-band gain-flattened EDTFA we developed using a fiber-Bragg-grating-type gain equalizer. We achieved a gain of 25.3 dB and a noise figure of less than 6 dB with a slight gain excursion of 0.6 dB over a wide wavelength range of 1561-1611 nm. The total output power of the EDTFA module was 20.4 dBm and its power conversion efficiency reached 32.8%.     

0.18-/spl mu/m CMOS push-pull power amplifier with antenna in IC package

A novel architecture of power amplifier with antenna implemented in a ceramic ball grid array (CBGA) package is presented. The monolithic power amplifier designed in a standard 0.18- /spl mu/m CMOS technology offers 19.5 dBm maximum output power at 5.2 GHz to the antenna with the PAE of 32%. The antenna integrated in the CBGA package achieves impedance bandwidth of 3.86% and gain of 2 dBi at 5.2 GHz. Results demonstrate the feasibility of using this innovative configuration to the design of single-chip 5 GHz transmitter front-end.     

PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit

A personal communications service/wide-band code division multiple access (PCS/W-CDMA) dual-band monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting a newly proposed on-chip linearizer. The linearizer is composed of the base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the base node of the active bias transistor. The linearizer enhances the linearity of the power amplifier effectively for both PCS and W-CDMA bands with no additional DC power consumption, and has negligible insertion power loss with almost no increase in die area. It improves the input 1-dB gain compression point by 18.5 (20) dB and phase distortion by 6.1/spl deg/ (12.42/spl deg/) at an output power of 28 (28) dBm for the PCS (W-CDMA) band while keeping the base bias voltage of the power amplifier as designed. A PCS and W-CDMA dual-band InGaP heterojunction bipolar transistor MMIC power amplifier with single input and output and no switch for band selection is embodied by implementing the linearizer and by designing the amplifier to have broad-band characteristics. The dual-band power amplifier exhibits an output power of 30 (28.5) dBm, power-added efficiency of 39.5 % (36 %), and adjacent channel power ratio of -46 (-50) dBc at the output power of 28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA) applications.     

A high gain, high output saturation power Pr/sup 3+/-doped fluoride fiber amplifier operating at 1.3 mu m

A high net gain of 30.1 dB at 1.309 mu m and an output saturation of 13 dBm are obtained using a Pr/sup 3+/-doped fluoride fiber amplifier pumped at 1.017 mu m. The critical Pr/sup 3+/ concentration at which concentration quenching begins to occur was obtained by fluorescence lifetime measurement. The Pr/sup 3+/ concentration should be less than 1000 ppm to suppress the concentration quenching by cross relaxation. A high signal output power of 17.8 dBm was extracted from the Pr/sup 3+/-doped fluoride fiber. The Pr/sup 3+/-doped fluoride amplifier shows good potential for use in 13. mu m telecommunication systems.<>     

A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.     

Ultra-broadband 20.5-31 GHz monolithically-integrated CMOS power amplifier

A fully monolithically-integrated power amplifier with a bandwidth (-3 dB) from 20.5 to 31 GHz was realised in a 0.13 /spl mu/m standard CMOS technology. A maximum power added efficiency of 13% with a corresponding output power of 13 dBm was achieved at 25.7 GHz with 1.5 V supply voltage.     

A 1.25-gb/s burst-mode receiver for GPON applications

This paper presents a 1.25-Gb/s burst-mode receiver (BMRx) for upstream transmission over gigabit passive optical networks (G-PONs). The dc-coupled receiver uses a unique arrangement of three limiting amplifiers to convert the bursty input signal to a current mode logic output signal while rejecting the dc offset from a preceding transimpedance amplifier. Peak detectors extract a decision threshold from a sequence of 12 successive nonreturn-to-zero (NRZ) 1's and 12 successive NRZ 0's received at the beginning of each packet. Automatic compensation of the remaining offsets of the BMRx is performed digitally via digital-to-analog converters. The chip was designed in a 0.35-/spl mu/m SiGe BiCMOS process. The receiver contains an APD with a gain of 6 and a transimpedance amplifier and shows a sensitivity of -32.8 dBm and a dynamic range of 23.8 dB. A sensitivity penalty of 2.2 dB is incurred when a packet with average optical power of -9 dBm precedes the packet under consideration, the guard time between the packets being 25.6 ns. The BMRx includes activity detection circuitry, capable of quickly detecting average optical levels as low as -35.5 dBm. The performed measurements prove that the receiver meets the G-PON physical media dependent layer specification defined in ITU-T Recommendation G.984.2.     

Plug-in type 1.3-/spl mu/m fiber amplifier module for rack-mounted shelves

We have successfully developed a plug-in type PDFA module for rack mounted shelves which is assembled on a printed-board. In this module, we use a newly developed Pr/sup 3+/-doped high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber and wavelength stabilized 1.017-/spl mu/m laser diodes (LDs). We have obtained a small-signal gain of 24 dB and a noise figure of 6.6 dB at 1.30 /spl mu/m with an LD drive current of 240 mA/spl times/2. We achieved an output power of 10 dBm with a signal input power of 0 dBm. The total power consumption of this module, including that of a Peltier cooler, was 3.5 W when the LD drive current was 240 mA/spl times/2.