用ARM926EJ-S处理器实现JPEG图像软件解码

在分析JPEG编解码原理后,提出基于ARM926EJ-S处理器的JPEG软件解码方案,并对各个模块算法进行优化,改进后的JPEG解码器平均解码性能有了较大提升。     

基于ARM926EJ-S的MPEG-4软解码器的优化与实现

MPEG-4解码器的软件实现是嵌入式应用领域的热门研究课题。但是由于MPEG-4解码系统庞大的数据处理量和嵌入式微处理器处理能力不高的矛盾致使软解码的速度非常低。对此,根据MPEG-4软解码系统的特性及当前嵌入式领域主流微处理器ARM核的特点,研究了一种基于ARM9微处理器上实现MPEG-4软解码的算法优化方法和实现方案。详细介绍了优化的三个方面,包括软件结构优化;对数据处理较多模块编写ARM汇编函数替换;对关键模块寻找快速算法和并行处理算法等。实验结果表明优化后的算法在ARM9微处理器平台上对QVGA格式的MPEG-4码流播放速度由优化前的10 f/s提高到了37 f/s,完全实现了流畅播放,具备很高的实用价值。     

基于DM642DSP的MPEG-4视频解码算法优化设计

讨论并实现了基于DSP的MPEG-4视频实时解码算法。首先系统级优化算法,修改适于DSP的数据结构以减小算法对存储器的要求,然后有效分配片上核心内存,针对DSP自身的特点,对EDMA、缓存Cache、线性汇编优化和软件流水及CCS优化工具等方面做专门优化。实验结果证明,该优化算法可实现多路视频图像的实时解码,在码流300 kb/s、CIF分辨率I、BP模式条件下,MPEG-4解码算法速度可达190-200 f/s。     

基于ARM926的MPEG-4视频编解码系统设计

简介了MPEG-4的特点和视频部分的基本内容,描述了实现编码和解码的运行环境和测试平台以及详细流程,着重介绍了基于ARM926EJ处理器的MPEG-4视频编解码系统的原理及实现,该系统适用于视频监控领域。     

基于TMS320C6000的MPEG-4视频实时解码优化设计

介绍在TMS320C6000系列DSP上实现MPEG-4视频实时解码的优化方法。先对OpenDivxDecore做数据结构优化,有效减少了Decore对存储空间的要求。在此基础上,针对DSP的特点,在内外存储器分配、DMA数据搬移、软件流程等方面做专门优化。优化后的代码在TIC6711图像开发板(IDK)上运行的实验结果表明,在码率为800Kbps视频格式为CIF352×288的条件下,MPEG-4解码速度可达30～45fps。     

利用微处理器实现MPEG-4视频解码

在分析ARMIT DMI结构基础上,详细阐述了如何对微处理器ARM7TDMI进行优化,以实现MPEG－4视频解码,并给出了实验效果。     

MPEG-2视频解码及硬件实现

本文简明介绍了MPEG-2的系统结构及系统流的解码，着重分析了视频解码器的功能原理及其实现方案，并就视频解码芯片CL9100的功能作一些介绍。     

基于DSP的MPEG-4视频编码软件优化设计

采用TMS320C6201 DSP芯片实现了实时的MPEG—4视频编码器，在扼要介绍了MPEG—4算法原理的基础上，探讨了软件优化的技术关键——代码优化方法，并给出了实验结果。     

基于TMS320C6416的MPEG-4视频解码卡设计

针对TMS320C6416的结构特点,介绍了一种用TMS320C6416来实现MPEG-4视频图像解码的方案,其中包括解码卡的结构、解码算法和算法优化等一系列问题.     

基于DSP的MPEG-4网络视频编码器实现

给出基于TMS320DM642实验平台的MPEG-4网络实时编码实现方法，阐述了系统实现结构框图，在分析DM642特点的基础上，讨论了网络视频编码器的实现和优化策略，并给出了较好的实验结果。     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

MPEG-4嵌入式视频解码系统的研究与实现

提出MPEG-4嵌入式视频解码系统的实现方案,分析MPEG-4嵌入式视频解码系统的结构。以SmartARM不起2200开发板为目标硬件平台,在μClinux操作系统基础上,实现了MPEG-4视频解码系统的在嵌入式平台上的移植,并对解码系统从算法和结构上进行优化。最后对系统进行测试,并给出了系统的实现效果。实验结果表明本设计实现了视频解码的要求并能取得较好的视觉效果。     

基于PC机的MPEG-4编码原理研究及实现

为了研究MPEG-4编码器的实现原理和影响编码效果的参数,这里简要介绍MPEG-4视频标准,详细分析形状编码、DC和AC预测、之字型扫描、游程编码和熵编码、运动估计与补偿等编码模块,调试并运行DIVX版本的MPEG-4 C语言编解码器,修改不同的编码参数,生成了不同大小的divx文件.实验结果表明,MPEG-4视频编码器的编码效果受各个编码参数的影响,透过参数调整可以达到最好的压缩效果.     

基于SSE2的MPEG-4视频快速解码研究

离散余弦逆变换是MPEG-4视频纹理解码中运算时间开销最大的部分.本文在快速离散余弦逆变换算法的基础上,引入针对多媒体数据流的SSE2并行计算技术.在保证图像质量的前提下大幅度提高了软件的解码速度.实验结果表明,该方法能有效地降低MPEG-4视频解码的时间开销,适合于NC环境下的视频分发应用.     

基于MPEG-4视频采集PCI板卡的设计与实现

介绍一种基于MPEG-4的视频压缩编码卡。该板卡为4路的编码PCI卡，将采集到的模拟视频图像以MPEG-4的方式进行压缩处理。使用标准PCI2．2的规范，完成有CPU控制板与编码PCI卡之间的通信，使CPU控制板通过一块桥芯片可以访问编码芯片内部寄存器，读出编码芯片压缩的MPEG-4的视频压缩流、音频压缩流。从而使压缩的MPEG-4数据完成远程传输或本地存贮。另一个是完成视频预览功能。该板卡为实现远程实时监控提供了必要的硬件设备，他以最新的MPEG-4压缩方式进行编码，对整个数字监控系统和视频网络传输系统提供了最优化的硬件设计，使视频数据数字化管理更加方便、可靠，也使整个系统在市场竞争中更具有活力。