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1.
NBTI导致的晶体管老化成为影响电路稳定性的主导因素,同时,降低电路的泄漏功耗是电路设计的目标之一。多米诺电路广泛应用在高性能集成电路中。本文提出了一种多米诺电路用来抑制NBTI引起的多米诺电路衰退并同时降低待机模式下的泄漏电流。在待机模式下,利用2个晶体管将标准多米诺电路的动态节点和输出节点同时上拉为电源电平,从而将保持器和输出反相器中的pMOS晶体管同时置为NBTI的恢复模式。使用全0输入向量和其中增加的一个晶体管的堆栈效应降低待机模式下多米诺电路的泄漏电流。实验表明针对NBTI效应,该方法降低了最多33%的性能衰退,并同时减少了最多79%的泄漏电流。  相似文献   

2.
一种容忍老化的多米诺门   总被引:2,自引:0,他引:2  
负偏置温度不稳定性引起的晶体管老化已经成为影响集成电路可靠性的重要因素。高扇入多米诺或门是高性能集成电路中常用的动态电路,而负偏置温度不稳定性降低了多米诺或门的噪声容限并增大了其传输时延。本文提出了保持器和反相器均带有补偿晶体管的多米诺或门结构,通过开启补偿电路,使电路在老化以后仍然能够保持其抗干扰能力和传输延时,有效的延长了多米诺电路的使用寿命。  相似文献   

3.
电平转换电路被广泛地应用于系统中不同电压域之间的信号传输,为了使其在使用中具备更高的可靠性,需要进行老炼试验来剔除早期失效,合理的老炼方案能够得到理想的结果,不合理的老炼方案不仅无法剔除早期失效,还会引入新的缺陷。从实际案例出发,通过不同的老炼方案,获得了方案之间的对比结果,并结合失效分析,得到了最优的老炼试验方案,具有一定的推广应用价值。  相似文献   

4.
当晶体管的特征尺寸减小到45 nm时,电路的可靠性已经成为影响系统设计一个关键性因素。负偏压温度不稳定性(NBTI)和泄露功耗引起的电路可靠性现象的主要原因,导致关键门的老化加重,关键路径延迟增加,最终使得芯片失效,影响系统的正常工作。为了缓解NBTI效应和泄露功耗对电路可靠性的影响,延长电路的使用寿命,文中提出了循环向量方法进行协同优化。在ISCAS85基准电路,利用本方法协同优化实验,NBTI效应平均延迟相对改善了10%,泄漏功耗平均降低了15%,证明了循环向量方法的可行性。  相似文献   

5.
提出一种占空比可调的高速电平转换电路,能够将频率高达1.33 GHz的低电压域信号提升至高电压域输出。在传统电平转换电路的基础上,增加了占空比调节电路,使得电路工作在不同I/O域时,通过调整接入的PMOS管数量来间接调整控制管的宽长比,进而实现占空比可调。增加了快速响应电路,引入首尾相接的反相器组,通过正反馈功能,加速实现电平转换。基于Global Foundry 14 nm CMOS工艺进行电路设计,采用SPECTRE软件进行仿真。仿真结果表明,该电路能够实现从0.9 V核心电压到2.5 V I/O电压的稳定转换,传播延时为225 ps,占空比为49.63%。当高电压域电压变换为1.8 V后,通过占空比调节电路,使占空比仍可保持在50%左右。  相似文献   

6.
<正> 随着计算机技术的高速发展,人类已经进入了数字时代。今天普通计算机的运算速度也已从上世纪的每秒钟千万次发展到了几十亿次。对于数字电路而言,适当降低供电电压,有利于运算速度的提升。早期的异步通讯RS232接口采用的的是正负12V的供电电压,抗干扰能力虽然较强,但是传输速率也是很低的,不超过1Mbps。目前生产的计算机芯片使用最多的是5V的供  相似文献   

7.
负偏置温度不稳定性引起的晶体管老化已经成为影响集成电路可靠性的重要因素.高扇入多米诺或门是高性能集成电路中常用的动态电路,而负偏置温度不稳定性降低了多米诺或门的噪声容限并增大了其传输时延.本文提出了保持器和反相器均带有补偿晶体管的多米诺或门结构,通过开启补偿电路,使电路在老化以后仍然能够保持其抗干扰能力和传输延时,有效的延长了多米诺电路的使用寿命.  相似文献   

8.
电路老化中考虑路径相关性的关键门识别方法   总被引:2,自引:0,他引:2  
65nm及以下工艺,负偏置温度不稳定性(NBTI)是限制电路生命周期,导致电路老化甚至失效的最主要因素。本文提出了基于NBTI的时序分析框架,在确定电路中老化敏感的潜在关键路径集合的基础上,通过考虑路径相关性确定老化敏感的关键门。本方法简单易行,在65nm工艺下对ISCAS基准电路的实验结果表明:在保障电路经10年NBTI效应仍满足相同的时序要求的前提下,本方法较同类方法能更加准确得定位关键门,且关键门的数量较少,从而可减少抗老化设计的成本。  相似文献   

9.
随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。  相似文献   

10.
出于性能、功耗和兼容性的考虑,芯片的核心电路与I/O电路一般采用不同的电源电压.文中设计了一种新型2.5V/5V双电源电压输出电路,此电路带有新型电平转换电路,能够将摆幅为0~2.5V的内部信号转换为摆幅为0~5V的输出信号.同时,文中所设计的输出电路只使用2.5V耐压的薄栅氧MOS器件,虽然在5V电压下工作,却没有栅氧过压问题.  相似文献   

11.
分析了石英晶体的等效模型和性能参数,设计了一款基于皮尔斯振荡器的8 MHz晶振电路,主要包括皮尔斯电路、使能控制及隔离电路、偏置电路和整形及电平移位电路.针对数字电路时钟为方波且数字电压域与模拟电压域不同的问题,设计了一个整形及电平移位电路,将晶体振荡器输出的正弦波整形成方波,且电路实现了双电压域工作.基于华宏0.11...  相似文献   

12.
This paper reports a voltage reference circuit in standard CMOS process. It exhibits excellent supply independency for a wide input voltage range, which is of great importance in telemetry-powered systems. This circuit is based on the well-known VGS-reference supply-independent current reference circuit, but it is designed to serve as a voltage reference. While the reference current generated by this circuit varies with the supply voltage, a self-compensating mechanism can be found in voltage-mode operation of the circuit that results in a supply-independent reference voltage. This supply independency is well observed in the static operation of the circuit over an extremely wide input range, as well as in its dynamic behavior for high frequency ripples on the input voltage. Based on the proposed idea, a multi-output voltage reference and a CMOS DC level shifter are also designed. The proposed voltage reference circuits have been fabricated using MOSIS 1.6 μm standard CMOS process. The basic voltage reference provides 957 μV/V static supply dependency, rejects input ripples of up to 8 MHz by 60± 3dB, and consumes only 15.8–36.9 μA when the input voltage varies in the range 2.6–12 V. Amir M. Sodagar received the B.S. degree from K.N. Toosi (KNT) University of Technology, Tehran, Iran, and M.S. and Ph.D. degrees from Iran University of Science & Technology (IUST), Tehran, Iran all in Electrical Engineering in 1992, 1995, and 2000, respectively. From 1992 to 2000 he was with S. Rajaee University as a Lecturer. After receiving the Ph.D. degree until 2002 he was with the NSF Engineering Research Center for Wireless Integrated Micro Systems (WIMS), Electrical Engineering & Computer Science (EECS) Dept., University of Michigan as a Post-Doctoral Research Fellow. From 2002 to 2004 he was with S. Rajaee University and KNT University of Technology as an Assistant Professor and an Adjunct Professor, respectively, and since 2004 he has been with the University of Michigan as an Associate Visiting Research Scientist. Dr. Sodagar was known as the Outstanding Electrical Engineering Graduate Student of the IUST in 1995, and receiv ed the IUST's Best Ph.D. Research Achievement Award in 2000. He was also the recipient of S. Rajaee University's Distinguished Faculty Member Award for “1998–1999” and “1999–2000” academic years, and S. Rajaee University's Distinguished Researcher Award for “2002–2003” academic year. He was involved in the design of integrated circuits in collaboration with the Center for Semiconductor Research and Fabrication from 1994 to 1995, VLSI Circuits & Systems Laboratory at the University of Tehran from 1997 to 1998, and EMAD Semicon Company from 1998 to 2000. He has authored one book, authored/co-authored more than 20 journal and conference papers, and served as the technical paper reviewer for several IEEE journals/transactions and also conferences. Dr. Sodagar's research interests are generally in the field of mixed-signal integrated circuit design, and focused on: integrated circuits for neural recording & stimulation, telemetry powering and control of implantable microsystems, frequency synthesizers, analog building blocks, and transistor-level implementations of digital logic families. Khalil Najafi (IEEE S '84, M '86, SM '97, F'00) received the B.S., M.S., and the Ph.D. degree in 1980, 1981, and 1986 respectively, all in Electrical Engineering from the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor. From 1986–1988 he was employed as a Research Fellow, from 1988–1990 as an Assistant Research Scientist, from 1990–1993 as an Assistant Professor, from 1993–1998 as an Associate Professor, and since September 1998 as a Professor and the Director of the Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan. His research interests include: micromachining technologies, micromachined sensors, actuators, and MEMS; analog integrated circuits; implantable biomedical microsystems; micropackaging; and low-power wireless sensing/actuating systems. Dr. Najafi was awarded a National Science Foundation Young Investigator Award from 1992–1997, was the recipient of the Beatrice Winner Award for Editorial Excellence at the 1986 International Solid-State Circuits Conference, of the Paul Rappaport Award for co-authoring the Best Paper published in the IEEE Transactions on Electron Devices, and of the Best Paper Award at ISSCC 1999. In 2003 he received the EECS Outstanding Achievement Award, in 2001 he received the Faculty recognition Award, and in 1994 the University of Michigan's “Henry Russel Award” for outstanding achievement and scholarship, and was selected as the “Professor of the Year” in 1993. In 1998 he was named the Arhtur F. Thurnau Professor for outstanding contributions to teaching and research, and received the College of Engineering's Research Excellence Award. He has been active in the field of solid-state sensors and actuators for more than twenty years, and has been involved in several conferences and workshops dealing with solid-state sensors and actuators, including the International Conference on Solid-State Sensors and Actuators, the Hilton-Head Solid-State Sensors and Actuators Workshop, and the IEEE/ASME Micro Electromechanical Systems (MEMS) Conference. Dr. Najafi is the Editor for Solid-State Sensors for IEEE Transactions on Electron Devices, an Associate Editor for the Journal of Micromechanics and Microengineering, Institute of Physics Publishing, and an editor for the Journal of Sensors and Materials. He also served as the Associate Editor for IEEE Journal of Solid-State Circuits from 2000–2004, and the associate editor for IEEE Trans. Biomedical Engineering from 1999–2000. He is a Fellow of the IEEE.  相似文献   

13.
热载流子注入(hot carrier injection,HCI)效应和负偏压温度不稳定性(negative biastemperature instability,NBTI)是集成电路中重要的前段器件工艺可靠性测试项目。通过引入工业统计学,详细讨论了在不同工艺制造情况或测试环境下HCI/NBTI效应可靠性差异的比较方法。这些对于HCI/NBTI测试比较方法的总结,有利于合理分析工艺可靠性测试结果,协助晶圆生产部门找出失效机理,不断改善工艺制程并保持工艺的稳定性。  相似文献   

14.
分析薄膜晶体管液晶显示(TFT-LCD)栅驱动芯片ASTLC5301A的原理,借助Pspice仿真工具进行驱动电路的设计,重点讨论芯片内部高低电平位移转换电路,提出改进型电平接口电路,完成高低压驱动管的尺寸和结构设计。  相似文献   

15.
本文以Schiffman 90°差分移相器为研究对象,采用补偿奇、偶模相速和考虑末端连接效应两方法,分析和设计了由两节阶梯型耦合线组成的微带差分移相器。实验结果表明:制作在ε_r=9.6的氧化铝陶瓷基片上的C波段该种移相器具有良好的宽频带性能。  相似文献   

16.
王佳妮  周泽坤  李颂  石跃  王卓  张波 《微电子学》2020,50(3):315-320
提出了一种新型低功耗、高稳态电平位移电路。该电路能将5 V输入电压转换为10 V输出电压,在电路的初态和电平转换过程中均保持高稳态。采用瞬态增强结构,能加速电平信号之间的转换,有效地减小了传输延迟,提高了电路稳定性。瞬态增强结构在稳定状态时不发挥作用,减小了静态功耗,获得了低功耗。基于标准0.35μm BCD工艺和多5 V LDMOS耐压器件,对该电平位移电路在5 MHz频率下进行验证。结果表明,动态功耗仅为24.8μA,上升沿响应速度仅为12.7 ns,下降沿响应速度仅为22.8 ns。该电路具有可靠性高、功耗低的优点。  相似文献   

17.
为了满足MHz以上频率的GaN半桥栅驱动系统的应用需求,提出了一种高速高可靠性低功耗的低FOM电平位移电路。串联可控正反馈电平位移电路通过仅在转换过程中减弱正反馈力度,实现了低传输延迟和高共模噪声抗扰能力,同时采用最小短脉冲电路设计以降低功耗。该电平位移电路基于0.5μm 80 V高压(HV)CMOS工艺进行设计与仿真验证,结果表明,电路具有960 ps的传输延时、50 V/ns的共模噪声抗扰能力和0.024 ns/(μm·V)的FOM值。  相似文献   

18.
邵瑞洁  吴之久  明鑫  王卓  张波 《微电子学》2024,54(4):564-569
在高压GaN半桥栅驱动系统应用中,需要通过电平位移电路来实现信号在不同电压域之间的转换。为了保证转换过程中的信号完整性,设计了一种面向GaN驱动的高噪声抗扰度电平位移电路。在半桥开关节点电压发生快速切换时,针对电路内部大寄生电容节点充放电导致输出误翻转的问题,采用交叉耦合方式抑制共模噪声电流传递,实现了较高的噪声抗扰度。另外,采用电压-电流转换技术提高了抗负压能力。基于0.8 μm 600 V高压BCD工艺进行电路设计。仿真结果表明,该电平位移电路平均传输延时为5.62 ns,dV/dt噪声抗扰度为200 V/ns,在6 V电源电压下允许开关节点负压低至-4.5 V。  相似文献   

19.
简要介绍了矢量移相器的原理、特点、基本结构,提出了一种新型的采用数学方式控制的矢量移相器。  相似文献   

20.
GaN半桥输出点电压在死区时间为负值,给GaN功率器件栅极驱动电路信号通信带来了挑战.通过研究驱动器电平移位锁存电路工作状态与半桥功率级输出节点电压跳变、死区时间负压之间的相互影响,设计了一种新型的零静态功耗电平移位电路及其误触发消除电路.电路采用100 V BCD 0.18μm工艺设计,在输入电压100V、开关频率5...  相似文献   

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