一个用于高速SerDes的基于0.18um CMOS工艺的6.25Gb/s均衡器

本文介绍了一种基于0.18mm CMOS工艺,适用于高速背板传输的6.25Gb/s均衡器。该均衡器由1抽头前馈均衡器(FFE)和2抽头判决反馈均衡器(DFE)组成,能够消除前向码间干扰和后向码间干扰。FFE中的延迟线采用了有源电感峰化技术,不仅增加了带宽,也节省了面积。基于CML的加法器,触发器和选择器的使用则提高了DFE的速度。测试结果表明,对于经过衰减达22dB的30英寸信道的6.25Gb/s数据,该均衡器能够很好地进行均衡。1.8V的电源电压下的功耗为55.8mW,包括焊盘在内的整个芯片面积为0.3*0.5 mm₂。     

基于SST驱动器的低功耗10 Gbit/s发射机

基于SMIC 40 nm CMOS工艺,提出了一种可适用于背板与芯片互连的10 Gbit/s低功耗发射机。该发射机由半率前馈均衡器、时钟信号接收电路和源串联终端(SST)驱动器组成。前馈均衡器采用半率结构,以降低发射端的时钟信号频率。通过对发射端信号进行预加重,消除了码间干扰的影响。改进了SST驱动器的输出阻抗校准电路,解决了输出阻抗在不同工艺角下的波动问题。在相同输出摆幅下,SST电压模式驱动器的功耗为传统电流模式(CML)驱动器的1/4。结果表明,发射机的数据率为10 Gbit/s,传输信道在5 GHz Nyquist频率处的衰减为14.2 dB。在1.1 V电源电压下,传输信道输出信号的眼高为147 mV,眼宽为79 ps。发射机的总功耗为20.6 mW。     

25～28 Gbit/s CMOS高灵敏度光接收机电路设计北大核心

基于65 nm CMOS工艺设计了一种25～28 Gbit/s具有自适应均衡和时钟数据恢复功能的光接收机电路。光接收前端采用低带宽设计，以优化接收机的灵敏度；采用判决反馈均衡器，以恢复低带宽前端引入的码间干扰。为了适应不同速率和工艺角引入的码间干扰，结合SS-LMS自适应算法，实现信号的自适应均衡。无参考时钟数据恢复电路采用鉴频环路拓宽频率捕获范围，同时将半速率鉴相器嵌入均衡器中，以降低功耗和成本。后仿真结果表明，在100 fF光电二极管的寄生电容条件下，接收前端最大增益达到66 dBΩ,25%带宽处的等效输入噪声电流为15.3 pA·Hz-1/2,光接收机灵敏度为-14.5 dBm。当电源电压为1.2 V时，光接收机的整体功耗为181.1 mW。     

应用于10 Gbit/s光通信及背板传输的自适应均衡器设计

描述了一种既可用于背板传输也可用于光纤通信的高速串行收发器前端均衡器的设计。为适应光信号在传播中的色散效应,使用前馈均衡器(FFE)加判决反馈均衡器(DFE)的组合,取代了背板通信中常用的连续时间线性均衡器(CTLE)和DFE的组合。设计使用3 pre-tap、3 post-tap和1个main tap的抽头组合方式,兼顾pre-cursor和post-cursor的信号失真,有效补偿范围为15 dB。补偿系数采用完全自适应算法调整,对FFE采用模拟MSE算法调整,DFE引擎采用1/16速率数字sign-sign最小均方差(LMS)算法实现。芯片使用UMC 28 nm工艺流片,输入信号频率为10 Gbit/s。     

一个用于背板通信的24Gb/s高速自适应组合均衡器

本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器（Continuous Time Linear Equalizer,CTLE）和2抽头判决反馈均衡器（Decision Feedback Equalizer,DFE）的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方（Least Mean Square,LMS）算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm²,在3.3V的电源电压下,功耗为624mW.     

一种25Gbit/s CMOS判决反馈均衡器设计

为满足高速光通信系统的应用，基于标准40 nm CMOS工艺设计了一款25 Gbit/s判决反馈均衡器(DFE)电路，采用半速率结构以降低反馈路径的时序要求。主体电路由加法器、D触发器、多路复用器和缓冲器组成，为了满足25 Gbit/s高速信号的工作需求，采用电流模逻辑(CML)进行设计。经过版图设计和工艺角后仿验证，该DFE实现了在25 Gbit/s的速率下可靠工作，能提供10 dB的均衡增益，峰-峰差分输出电压摆幅约为950 mV,眼图的垂直和水平张开度均大于0.9 UI,输出抖动小于3 ps,在1.1 V的电源电压下功耗为12.5 mW,芯片版图的面积为0.633 mm×0.449 mm。     

一种25 Gbit/s CMOS自适应判决反馈均衡器

基于65 nm CMOS工艺,设计了一种25 Gbit/s带有一个无限冲激响应抽头的自适应判决反馈均衡器。该均衡器中关键路径采用堆叠式选择器和锁存器组成的半速率预测式结构,以减小环路反馈延时。自适应模块采用改进的最小均方算法,以改善抽头系数的收敛性。输出缓冲采用改进的fT倍增结构,以提升带宽并具有预加重功能。仿真结果表明,当信号速率为25 Gbit/s时,该均衡器能够自适应地实现最高20 dB衰减量的补偿,输出抖动小于10 ps。1.2 V电源供电时,整体电路在不同工艺角下的平均功耗约为120.5 mW。     

基于系数可调FFE的10 Gb/s发送端的设计

采用SMIC 40 nm CMOS工艺,设计了一种工作在10 Gb/s的SerDes高速串行接口发送端电路,并创新性地提出了一种系数可调的FFE结构,使电路能适用于不同衰减的信道。电路主要模块为复接器、3阶FFE均衡器。复接器采用经典半速率结构,使用数字模块搭建,降低了功耗,并通过设计使采样时钟位于输入的最佳采样点,抑制了毛刺的产生。FFE均衡器采用结构简单的TSPC类型D触发器、低功耗的选择器和系数可调节抽头加法电路,使信号达到均衡效果,补偿信道的衰减。仿真结果显示,电路稳定工作于10 Gb/s,在1.1 V电源电压下功耗仅为30 mW。     

一种高速串行信号线性均衡电路

设计了一种高速串行信号连续时间线性均衡器。采用有源电感负载结构,结合高频与全频通路信号求和技术来实现高速串行信号均衡。电路具有面积小、功耗低、利于集成等优点。采用65 nm CMOS工艺进行设计,1.2 V电源供电,可对经过80 cm长的衰减信道、且传输速率为14 Gbit/s的信号进行补偿,实现6.24 dB@10.96 GHz的补偿。该均衡器将输出端信号眼图水平方向抖动减小至0.25UI,功耗数据率比低至0.399 mW·s/Gbit,设计版图面积为0.09 mm²。     

80 Gbit/s PAM4光接收机低噪声模拟前端电路设计

采用UMC 28 nm CMOS工艺,设计了一款应用于光接收机、工作在80 Gbit/s PAM4的低噪声模拟前端电路(AFE)。对噪声和带宽进行折中设计,采用了跨阻放大器(TIA)级联连续时间线性均衡器(CTLE)技术和输入电感峰化技术。为了更好地控制低频增益,进一步拓展带宽,采用了跨导跨阻(gm-TIA)结构的VGA。在输入电容100 fF和供电电压1.2 V下,实现的跨阻增益为48.5 dBΩ,带宽为36.1 GHz,平均等效输入噪声电流为22.6 pA/Hz,功耗为14.5 mW。     

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally     

A 5 Gb/s CMOS adaptive equalizer for serial link

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process.The circuit consists of the combination of equalizer amplifier,limiter amplifier and adaptation loop.The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics.In addition,an offset cancellation loop is used to alleviate the offset influence of the signal path.The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply.Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.     

Electrical equalization for advanced optical communication systems

We investigate equalizers for electronic dispersion compensation (EDC) of dispersion limited optical fibre communication links in combination with different modulation formats. We show that the performance of conventional equalizers including feedforward equalizer (FFE) and decision feedback equalizer (DFE) are fundamentally limited by the nonlinearity of square-law detection of the photodiode in direct detection systems. Advanced modulation formats such as differential phase shift keying (DPSK) and optical duobinary further enhance this kind of nonlinearity and degrade further FFE/DFE performance. However, nonlinear FFE–DFE and maximum likelihood sequence estimation (MLSE) take into account the mitigation of nonlinear inter symbol interference (ISI) and hence can achieve much better performance. We show that in contrast to other modulation formats, optical single sideband modulation results in approximately linear distortions after detection and thus a simple linear FFE equalizer can achieve good compensation.     

A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage.The receiver occupies 300×500/μm2.With the novel half rate period calibration clock data recovery(CDR)circuit,the receiver consumes 52 mW power.The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer(CTLE)and decision feedback equalizer(DFE).     

An area-efficient maximum-ratio-combining diversity receiver in 90 nm CMOS for free-space optical links

This paper presents a low-power imaging diversity front-end receiver employing the maximum-ratio-combining algorithm for free-space optical communication. It consists of seven signal channels and an output stage, each channel has a front-end transimpedance amplifier, a signal-to-noise ratio (SNR) estimator and a variable gain amplifier (VGA). The imaging receiver circuit was implemented in a 90 nm CMOS process. The maximum-ratio weighting is achieved with the SNR estimator and variable gain amplifier (VGA), which provides the signal with a gain proportional to the signal amplitude. The maximum ratio combining feature was demonstrated with two channels driven by photodiode emulation circuits for electrical characterization. The power dissipation for the whole chip is 43 mW from a single 1.2 V supply.     

A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFEfor magnetic recording

A continuous-time forward equalizer with one adaptive zero and a seventh-order linear-phase low-pass filter are described. The forward equalizer cancels precursor intersymbol interference (ISI). A mixed-signal four-tap RAM decision-feedback equalizer (DFE) is also included on the prototype to cancel the postcursor ISI. Both precursor and postcursor ISI are canceled in the analog domain. The adaption is done digitally. The low-pass filter and forward equalizer together occupy 6.7 mm² in a 1 μm CMOS process. They dissipate 280 mW from a 5 V supply when operating at 80 Mb/s. Including the RAM-DFE, the entire chip occupies 11.2 mm² and dissipates 630 mW     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10⁻⁹. The total active area is 0.21 mm² and the ADC consumes 76 mW from a 1.2-V supply.