一种14位100 MS/s的流水线模数转换器

设计了一种14位100 MS/s的流水线模数转换器(ADC)。采样保持电路与第1级2.5位乘法数模转换器(MDAC1)共享运放,降低了功耗。提出了一种改进的跨导可变双输入开关运放,以满足采样保持和MDAC1对运放的不同要求,并消除记忆效应和级间串扰。ADC后级采用5级1.5位运放共享结构。基于0.18 μm CMOS工艺,ADC核心面积为1.4 mm²。后仿真结果表明,在1.8 V电源电压下,当采样速率为100 MS/s、输入信号频率为46 MHz时,ADC的信噪比(SNR)为82.6 dB,信噪失真比(SNDR)为78.7 dB,无杂散动态范围(SFDR)为84.1 dB,总谐波失真(THD)为-81.0 dB,有效位数(ENOB)达12.78位。ADC整体功耗为116 mW。     

12bit10MS/s流水线结构模数转换器

介绍了12 bit,10 MS/s流水线结构的模数转换器IP核设计。为了实现低功耗,在采样电容和运放逐级缩减的基础上,电路设计中还采用了没有传统前端采样保持放大器的第一级流水线结构,并且采用了运放共享技术。瞬态噪声的仿真结果表明,在10 MHz采样率和295 kHz输入信号频率下,由该方法设计的ADC可以达到92.56 dB的无杂散动态范围,72.97 dB的信号噪声失调比,相当于11.83个有效位数,并且在5 V供电电压下的功耗仅为44.5 mW。     

一种低功耗14位10MS/s流水线A/D转换器

基于0.6μm BiCMOS工艺,设计了一个低功耗14位10MS/s流水线A/D转换器.采用了去除前端采样保持电路、共享相邻级间的运放、逐级递减和设计高性能低功耗运算放大器等一系列低功耗技术来降低ADC的功耗.为了减小前端采样保持电路去除后引入的孔径误差,采用一种简单的RC时间常数匹配方法.仿真结果表明,当采样频率为10MHz,输入信号为102.5kHz,电源电压为5V时,ADC的信噪失真比(SNDR)、无杂散谐波范围(SFDR)、有效位数(ENOB)和功耗分别为80.17dB、87.94dB、13.02位和55mW.     

一种嵌入式10位2MS/s逐次逼近模数转换器

设计了一种10位2 MS/s嵌入式逐次逼近结构ADC。为提高ADC精度,其中DAC采用电压和电荷按比例缩放混合结构,比较器使用了输入失调校准和输出失调校准技术。采用TSMC0.18μm1P6M数字CMOS工艺进行流片验证,整个ADC核面积仅为0.9×0.6 mm2。测试结果表明,在2 MHz采样率、输入信号为180 kHz正弦信号情况下,该ADC模块具有8.51位的有效分辨率,最大微分非线性为-0.8~+0.7LSB,最大积分非线性为-1.7~+1.5 LSB,而整个模块的功耗仅为1.2 mW。     

12位200MS/s交织A/D转换器设计

介绍了一个面向3G/4G LTE通信及雷达等应用的12位200 MS/s的高速低功耗A/D转换器(ADC).采用交织运放共享技术,可节省功耗,同时减小不同通道之间的增益失配、失调失配和带宽失配,提高ADC的性能.为了提高ADC的高频性能并避免时钟采样偏差带来的两路通道失配问题,采用一个工作在200 MS/s采样频率的统一的采样保持电路.芯片采用HJTC0.18 μm 1P6M CMOS的工艺制造,核心电路面积为1.6×4 (mm2),电源电压2.0V.流片测试结果表明,在4.9 MHz的输入频率下,无杂散动态范围(SFDR)为83.1 dB,信号噪声失真比(SNDR)为59.6 dB,模拟核心电流为120mA,FOM1和FOM2值仅为0.08 pJ/step和1.25 pJ/step.     

一种1.8V 10位100Ms/s流水线模数转换器设计

针对自举开关中的寄生效应和导通电阻的非线性问题提出了一种新的低压低电阻的自举开关.同时利用增益增强技术设计高直流增益和高单位增益带宽的运放,从而保证采样保持电路和子级电路的性能.基于以上技术,设计了一个10位100Ms/s流水线模数转换器,该模数转换器用0.18μm CMOS工艺流片验证.经测试,该模数转换器可以在采样率为100MHz,输入频率分别为在6.26和48.96MHz的情况下分别获得54.2和49.8dB的信噪比.     

一种1.8V 10位100Ms/s流水线模数转换器设计

针对自举开关中的寄生效应和导通电阻的非线性问题提出了一种新的低压低电阻的自举开关.同时利用增益增强技术设计高直流增益和高单位增益带宽的运放,从而保证采样保持电路和子级电路的性能.基于以上技术,设计了一个10位100Ms/s流水线模数转换器,该模数转换器用0.18μm CMOS工艺流片验证.经测试,该模数转换器可以在采样率为100MHz,输入频率分别为在6.26和48.96MHz的情况下分别获得54.2和49.8dB的信噪比.     

一种10位200 kS/s 65 nm CMOS SAR ADC IP核

该文基于65 nm CMOS低漏电工艺,设计了一种用于触摸屏SoC的8通道10位200 kS/s逐次逼近寄存器型(Successive Approximation Register,SAR) A/D转换器(Analog-to-Digital Converter,ADC) IP核。在D/A转换电路的设计上,采用7MSB (Most-Significant-Bit) + 3LSB (Least-Significant-Bit) R-C混合D/A转换方式,有效减小了IP核的面积,并通过采用高位电阻梯复用技术有效减小了系统对电容的匹配性要求。在比较器的设计上,通过采用一种低失调伪差分比较技术,有效降低了输入失调电压。在版图设计上,结合电容阵列对称布局以及电阻梯伪电阻包围的版图设计方法进行设计以提高匹配性能。整个IP核的面积为322m267m。在2.5 V模拟电压以及1.2 V数字电压下,当采样频率为200 kS/s,输入频率为1.03 kHz时,测得的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)和有效位数(Effective Number Of Bits,ENOB)分别为68.2 dB和9.27,功耗仅为440W,测试结果表明本文ADC IP核非常适合嵌入式系统的应用。     

采用改进型1.5位/级结构的10位100MHz流水线模数转换器

介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器. 测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在100MHz输入时钟下,输入信号为57MHz的奈奎斯特频率时,信噪失真比仍然可以达到51dB. 模数转换器的差分非线性和积分非线性分别为0.3LSB和1.0LSB. 电路采用0.18μm 混合信号CMOS工艺实现,芯片面积为0.76mm2.     

采用改进型1.5位/级结构的10位100MHz流水线模数转换器

介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器.测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在100MHz输入时钟下,输入信号为57MHz的奈奎斯特频率时,信噪失真比仍然可以达到51dB.模数转换器的差分非线性和积分非线性分别为0.3LSB和1.0LSB.电路采用0.18μm混合信号CMOS工艺实现,芯片面积为0.76mm2.     

一种应用于无线局域网接收机的1.2伏双通道10位55nm CMOS流水线模数转换器

A power-efficient technique for pipeline analog-to-digital converters(ADCs) is proposed. By sharing amplifiers between I/Q channels, the power dissipation of the ADCs is reduced by almost one-half compared to conventional topologies, which makes this technique suitable for low-power direct-conversion WLAN receivers. A dual-channel ADC test chip is fabricated in 55 nm CMOS technology. The 10 bit ADC with on-chip reference generators dissipates 19.2 mW per channel from a 1.2 V supply. At an 80 MS/s sample rate, the measured spuriousfree dynamic range, signal-to-noise and distortion ratio, and corresponding effective number of bits are 69.5 dB, 56.8 dB and 9.14 bits with a 1 MHz input frequency(fin/, and 61.3 dB, 56.5 dB and 9.09 bits with a 15 MHz fin, respectively. The active area is 1.01 0.77 mm2.     

一种16.9 mW 10 bit 50 Msample/s 流水线ADC IP核设计

设计了一个10位50 Msample/s流水线ADC IP核.采用SMIC 0.25 μm 1P5M数字CMOS工艺,通过使用运算放大器共享技术、电容逐级缩减技术和对单元电路的优化,使得整个IP核面积仅为0.24 mm2.仿真结果表明,在50 MHz采样率、输入信号为2.04 MHz正弦信号情况下,该ADC模块具有8.9 bit的有效分辨率,最大微分非线性为0.65 LSB,最大积分非线性为1.25 LSB,而整个模块的功耗仅为16.9 mW.     

一个低电压低功耗10位30MS/s流水线A/D转换器

实现了一个10位精度,30MS/s,1.2V电源电压流水线A/D转换器,通过采用运放共享技术和动态比较器,大大降低了电路的功耗。为了在低电源电压下获得较大的摆幅,设计了一个采用新颖频率补偿方法的两级运放,并深入分析了该运放的频率特性。同时还采用了一个新的偏置电路给运放提供稳定且精确的偏置。在30MHz采样时钟,0.5MHz输入信号下测试,可以得到8.1bit有效位的输出,当输入频率上升到60MHz(四倍奈奎斯特频率)时,仍然有7.9bit有效位。电路积分非线性的最大值为1.98LSB,微分非线性的最大值为0.7LSB。电路采用0.13μmCMOS工艺流片验证,芯片面积为1.12mm2,功耗仅为14.4mW。     

一种12位20 kS/s功耗调制算法SAR ADC

针对时域稀疏信号中的心电信号(ECG)、脑电信号(EEG)在大部分时间内幅度变化缓慢且周期性变化的特性,提出了一种带信号区间预测窗口的功耗调制型逐次逼近模数转换算法。采用该算法,可大幅减少SAR ADC中稀疏信号在低频部分的平均量化功耗,实现整体功耗的降低。在此理论基础上,设计了一种非二进制冗余校正、功耗调制型12位20 kS/s SAR ADC。该ADC采用55 nm CMOS工艺进行流片,在0.6 V电源电压下,功耗低至204 nW,功耗优值FoM最低为6.28 fJ/(conv·step)。     

一种采用改进放大器的12位40兆采样率的流水线模数转换器

本文设计实现了一种采用改进放大器的12位40兆采样率的流水线模数转换器。基于该模数转换器的结构,本文分析了影响模数转换器的精度的放大器非理想因素,并提出了针对放大器的补偿技术。该技术消除了增益提高技术和开关电容共模反馈结构对放大器的带宽和相位裕度的限制。整个模数转换器使用0.35μm标准CMOS工艺设计制作。测试结果表明,该模数转换器能够在2V输入范围内,40兆赫兹采样时钟下实现60.5dB信噪失真比和74.5dB的无杂散动态范围。     

A 12-bit,40-Ms/s pipelined ADC with an improved operational amplifier

This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter(ADC) with an improved high-gain and wide-bandwidth operational amplifier(opamp).Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC's resolution.Then,the compensation techniques of the ADC's opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.     

一种基于65 nm CMOS工艺的10位10 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种10位10 MS/s逐次逼近型模数转换器(SAR ADC)。采用全差分的R-C组合式DAC网络结构进行设计,提高了共模噪声抑制能力和转换精度。与全电容结构相比,R-C组合式DAC网络结构有效减小了版图面积。DAC中各开关的导通采用对称的开关时序,使比较器差分输入的共模电平保持为固定值,降低了比较器的失调电压,提高了ADC的线性度。在2.5 V模拟电源电压和1.2 V数字电源电压下,使用Spectre进行仿真验证,测得DNL为0.5 LSB,INL为0.8 LSB;在输入信号频率为4.990 2 MHz,采样频率为10 MHz的条件下,测得电路的有效位数为9.63位,FOM为0.04 pJ/conv。     

An 8 bit, 100 kS/s,switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm². The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×10²⁰, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.     

一款应用于生物传感器的1.2V-600nW 12bit 2kS/s的增量型模数转换器

This paper presents an ultra-low power incremental ADC for biosensor interface circuits.The ADC consists of a resettable second-order delta–sigma(°/ modulator core and a resettable decimation filter.Several techniques are adopted to minimize its power consumption.A feedforward path is introduced to the modulator core to relax the signal swing and linearity requirement of the integrators.A correlated-double-sampling(CDS)technique is applied to reject the offset and 1/f noise,thereby removing the integrator leakage and relaxing the gain requirement of the OTA.A simple double-tailed inverter-based fully differential OTA using a thick-oxide CMOS is proposed to operate in the subthreshold region to fulfill both an ultra-low power and a large output swing at 1.2 V supply.The signal addition before the comparator in the feedforward architecture is performed in the current domain instead of the voltage domain to minimize the capacitive load to the integrators.The capacitors used in this design are of customized metal–oxide–metal(MOM) type to reach the minimum capacitance set by the k T =C noise limit.Fabricated with a 1P6 M 0.18 m CMOS technology,the presented incremental ADC consumes600 n W at 2 k S/s from a 1.2 V supply,and achieves 68.3 d B signal to noise and distortion ratio(SNDR) at the Nyquist frequency and an FOM of 0.14 p J/conversion step.The core area is 100120 m2.