静态煅烧法除SiC微粉中碳杂质的工艺研究

由于SiC在电子半导体方面有较大应用,纯度要求就成为主要限制,尤其是碳杂质的影响。本实验对SiC微粉首先经过不同温度的煅烧测定烧失率确定最佳煅烧温度,然后在最佳煅烧温度下通过不同保温时间测定烧失率确定最佳保温时间,对粉体进行DTA-TG测定分析样品质量变化与温度的关系,最后对实验前后的样品进行XRD物相分析,最终得到除碳最佳煅烧温度900℃,最佳保温时间3h。     

多层瓷介电容器端电极制备工艺对端电极附着力影响研究

研究了多层瓷介电容器(MLCC)端电极制备环节中产品翻边宽度、端电极底银层厚度、烧端峰值温度、峰值温度保温时间及烧端装载密度对产品端电极附着力的影响.结果显示,随着翻边宽度和底银层厚度的增加,产品相应的端面结合强度随之提升,当翻边宽度为0.5 mm、底银层厚度为26μm左右时,产品的抗弯曲性能>8 mm,平均极限抗剪切...     

PTC欧姆铝电极浆料印烧工艺对元件性能的影响

以In/Ga电极作为参考电极,研究讨论了铝电极厚度对最终PTC元件性能的影响,并得出了最佳厚度参数。采用差热分析法,观察了在升温过程中铝电极的物理化学变化,并详细讨论了影响铝电极烧渗过程的三个重要参数:升温速度,最高烧渗温度及保温时间与元件性能的关系。得出在本电极组成条件下,最佳工艺参数:丝网目数为220目,升温时间为10 min,最高烧渗温度为660℃,保温时间为10 min。     

用校温环改善窑炉烧成产品质量

不论是电子陶瓷用粉体还是电容器、电阻器、电感器之类的电子陶瓷元件,对电性能的要求都较高。在配方和生产工艺相对固定的情况下,烧制品的累积热效应是直接影响产品电性能的因素,而热效应主要是烧成温度、保温时间和烧成气氛的综合体现。不同的烧成温度、保温时间和烧成气氛会烧结出不同性能     

工艺对钛酸铋钙基陶瓷性能的影响

采用正交实验优化了各氧化物掺杂CaBi4Ti4O15(CBT)陶瓷的最佳配方。A、B位复合掺杂改性效果比A位或B位掺杂改性明显。研究了预合成温度、保温时间、烧结温度和烧结方式对CBT基陶瓷性能的影响规律及其机理。结果表明:在850℃预合成,保温3h,1130℃Al2O3埋烧工艺条件下,研制出介质损耗为0.0055,相对介电常数为163.60,烧成收缩率为12.1%的陶瓷试样。     

气流闩式速冷隧道窑炉

<正> 陶瓷生产过程中的烧成工艺直接关系到所需主晶相能否形成以及已长成的晶粒的尺寸能否得到控制的问题。就烧成工艺而言,主晶相的形成取决于烧结温度和保温时间;晶粒尺寸控制则取决于保温时间和冷却速度。作者认为:由瓷料、烧结温度和保温时间确定的主晶相的形成,往往容易通过试烧试     

Ni/Cu电极MLCC烧端工艺的研究

通过对烧端工艺的详细研究,给出了最佳工艺参数:烧端温度为850～880℃,保温10min;用N2/O2混合气,在排胶段保持φ(O2)为300×10–6,在高温烧结段采用φ(O2)为10×10–6;600℃以下的升温速率控制在30～40℃/min,600℃以上的升温速率控制在50～60℃/min。在上述工艺条件下,选用合适的链式连续炉,可以得到端头性能良好的MLCC产品。     

一个高精度低温漂的带隙基准源

文章对传统典型CMOS带隙电压基准源电路分析和总结,重点分析了温度补偿原理。在对传统温度补偿技术改进的基础上,采用低失调电压运算放大器,融合了熔丝烧写调整电压技术,提出了一个温漂低于15×10-6℃-1的改进型带隙基准源电路。整个电路采用CSMC0.5μm工艺设计,采用Hspice进行仿真。为补偿工艺偏差,输出电压及输出电压的温漂均可通过铝熔丝烧写来调整。     

MLCC端电极Sn镀层的焊接失效分析

针对多层陶瓷电容器(MLCC)端电极Sn镀层的可焊性失效问题,运用SEM和能谱仪对Sn镀层进行微观结构和成分分析,找出了失效的主要原因,并提出了改进意见。在对MLCC三层端电极中的底层Ag端浆的烧渗过程中,由于烧渗工艺不合理,Ag浆中出现玻璃料物质的溢出,造成电镀Sn时Sn层不连续、不致密,以至MLCC端电极的可焊性变差。通过设计合理的烧渗银温度曲线可较好地解决MLCC端电极Sn镀层的焊接失效问题。     

通信整流器的保护及协调

介绍通信整流器的输出端保护，并从设计角度对电流限制、功率限制和充电电压进行讨论。     

一种新型无运放CMOS带隙基准电路

介绍了带隙基准原理和常规的带隙基准电路,设计了一种新型无运放带隙基准电路。该电路利用MOS电流镜和负反馈箝位技术,避免了运放的使用,从而消除了运放带隙基准电路中运放的失调电压和电源抑制比等对基准源精度的影响。该新型电路比传统无运放带隙基准电路具有更高的精度和电源抑制比。基于0.18μm标准CMOS工艺,在Cadence Spectre环境下仿真。采用2.5V电源电压,在-40℃～125℃温度范围的温度系数为6.73×10-6/℃,电源抑制比为54.8dB,功耗仅有0.25mW。     

A microprocessor-based firing circuit for thyristors working undera three-phase variable-frequency supply

A microprocessor-based firing scheme for controlling antiparallel-connected thyristors working under a three-phase variable frequency supply is presented. The firing angle is controlled by microcomputer software. The desired firing angle is given to the microprocessor and is then kept constant irrespective of supply frequency. This is achieved by measuring the frequency of one-phase (or line-to-line) voltage at every supply voltage cycle and accordingly adjusting the required time delay to get the desired firing angle for the thyristors of each phase. The required hardware is considerably reduced by using a zero-crossing detector for only the one-phase (or line-to-line) voltage of the three-phase supply. The firing instants of the thyristors connected to the other two phases are adjusted relative to the calculated instant of firing for the thyristors connected to the measured phase. The hardware and software used to implement the firing scheme are described     

Rise-time effects in grounded gate nMOS transistors under transmission line pulse stress

In this paper, the clamping voltage of a grounded gate nMOS transistor (ggnMOSt) under transmission line pulse (TLP) stress has been analysed in detail by means of a mixed-mode simulator. We show that the breakdown voltage of the ggnMOSt measured in static conditions could underestimate the maximum voltage across the protection structure obtained by TLP stress, depending on the rise time of the applied pulse. In particular, the smaller the rise time, the larger the peak reached for the drain voltage. In this paper, we will show that this can be attributed to the charging of the overlap capacitance. The influence of the LDD implant option with respect to the standard implant has also been investigated. The relationship between the maximum clamping voltage and the triggering voltage of the parasitic bipolar transistor associated with the structure is explained. A simple analytical model describing the response of the device in the early phase of the forced pulse is presented.     

Experimental Determination of a More Powerful Burn-In

This paper describes an experiment in which it was determined that burn-in could be made more powerful (i.e., capable of precipitating more failures in a given burn-in period) by reducing the time spent at the high temperature extreme. The number of failures precipitated in burn-in using a cycle consisting of a 2-hour non-operating cold soak and a 2-hour operating heat soak were compared to those precipitated using a 2-hour non-operating cold soak and a 4-hour operating heat soak. The shorter cycles precipitated as many failures as the longer, for an equal number of cycles. The fact that the shorter cycle required two-thirds the chamber time of the longer cycle equates to more cycles, and hence more failures removed, in a given burn-in period.     

Microprocessor based harmonic elimination in chopper type ACvoltage regulators

A control strategy for firing instances in pulse-width-modulated (PWM) AC voltage regulators is presented. In this type of regulator, output voltage is controlled by varying the on/off time ratios of a series-controlled switch. Using a microprocessor as a controller makes it possible to vary firing instances at will according to a predetermined timing regime. One of these regimes, proposed here, involves adjusting firing instances so that selected dominant lower-order harmonics can be eliminated. This in turn leads to improved system power factor and efficiency. The theoretical principles used in evaluating firing instances are described, and experimental results verifying the analysis are presented     

High-PSR sync separator for TV signals

This paper presents a novel NTSC video sync separator (NSS) with a high-PSR (power supply rejection) bias generation circuitry (BGC) which comprises a temperature compensation circuitry. The proposed BGC utilizes step-down regulators and a bandgap-based bias with cascode current control. The clamping voltages required for sync separation from an NTSC signal are generated. Detailed PSR analysis of the proposed BGC is also derived to circumscribe the clamping voltage variation. The proposed design is carried out using 0.35 μm 2P4M CMOS process. The measurement results verify that the HSYNC, the composite signal, and the Line 21 caption data can be separated successfully even if a 1 V noise is coupled in the supply voltage. The measured power consumption of the proposed chip is 31.92 mW.     

一种无运放电流模式带隙基准设计

为满足集成电路中低功耗／低温度系数的要求,基于负反馈钳位原理,采用分段线性补偿技术,通过在高低温度段分别插入非线性电流修正项对基准进行了曲率补偿,得到一种新型的无需运放的曲率补偿电流模式带隙电压基准源。仿真得到典型工艺下电路在室温27℃,工作电压4．5V下输出电压1．25062V,工作电流小于38pA,功耗小于170μW。在-40～＋150℃。宽温度范围内,基准电压在1．25018～1．25086V之间变化,温度系数约为2．86ppm／℃。     

一种简易红外通信装置的设计与实现

设计了一种简易数字控制红外通信装置,系统硬件部分由红外发射电路、红外接收电路和中转电路三部分组成。系统以STM32F051C4为控制核心,以红外线为载体,采用PWM调制技术、曼彻斯特编码方式,实现了语音和温度信号的实时传输。在保证系统稳定性的同时,通过采用低功耗器件、有效控制发射脉冲占空比等措施,提高中转节点的效率。系统完成硬件电路和软件程序后,经过实验测试,在输入800Hz的正弦信号,接收装置的输出电压有效值不低于0.4V时,红外光发射电路与红外光接收电路之间的传输距离最大为4m;在减小发射端输入信号的幅度至0V时,接收装置输出的噪声电压小于40mV;电路最大供电电流不超过20mA。     

50W高功率因数反激式开关电源箝位电路的研究

由于高PF(功率因数)宽电压反激式开关电源的变压器漏感会导致过压尖峰很高,需采用箝位电路吸收.目前常用的三种箝位电路有TD箝位(齐纳箝位)、RCD箝位、TRCD箝位电路,论文分别设计了三种50 W单级PFC的箝位电路.对三种箝位电路的箝位电压波形、EMI、温升和效率进行了测试,测试表明它们的温升、EMI依次降低;RCD和TRCD箝位的电源效率大于TD箝位的.     

Low voltage firing characteristics of a triggered vacuum gap

The triggered vacuum gap is a normally nonconducting device in which a high-current metal-vapor arc can be established by a suitable pulse of current to a triggering electrode. While this gap is well suited to switching applications at high voltage, it has properties which make it useful at low voltage as well. The operation of the triggered vacuum gap has, therefore, been studied in the range 100 to 1000 volts. It was found that, although the gap could be triggered with currents as low as 0.02 amperes, consistent triggering with firing delays less than a microsecond required trigger pulses of 10 amperes or more. Little or no dependence of firing time on main gap voltage was observed. Below a few hundred volts, however, the probability of establishing a stable main discharge with a short duration trigger pulse falls off rapidly with decreasing gap voltage. The polarity of the main gap voltage and of the trigger pulse strongly influenced the firing characteristics of the gap in the range studied. These effects are discussed in detail.