Localization and physical analysis of a complex SRAM failure in 90nm technology

In this paper the analysis process of a complex SRAM failure in 90nm technology is introduced in detail. Using a correlation method, it could be traced back to a failure with an increased supply current. With the help of MCT emission microscopy and thermal laser stimulation (TLS) the defects were localized at both edges of every failing SRAM block. Further inspection by passive voltage contrast (PVC) and atomic force prober (AFP) current imaging led to a localization down to contact level. In the TEM analysis high angle annular dark field scanning TEM (HAADF STEM) was used to obtain better material contrast. CoSi residues were found at the wall of spacers of the failing FETs. Further surface parallel TEM inspection confirmed the hypothesis of a new type of bridging defect, i.e. CoSi stringers along word lines in SRAM cells, which has not been observed before to our knowledge. The process adjustment in the fab to avoid this failure led to a significant yield improvement. The abstract should be 75-200 words long, summarizing the work and placing it in an appropriate context.     

The impact of tolerance on kill ratio estimation for memory

Spatially correlating in-line inspection data and post process electrical test data is an effective approach for estimating the yield impact of different defect types and/or process steps. An estimator for the probability that a particular type of defect kills an electrically testable structure, the kill ratio, has been described in the literature. This estimator may be used to predict the yield impact immediately after inspection, providing a number of benefits. It may also be used to generate a yield loss pareto by defect type. This paper introduces a new estimator for the kill ratio, which takes into account the impact of tolerance, a parameter setting the maximum distance between a defect and structure under which they are considered spatially correlated. This estimator was developed for memory (bitmap) data, where the tolerance is very large relative to the size of the structure. The tolerance is often increased to accommodate for misalignment between inspection tool sets and the electrical data. The problem with increasing the tolerance is that the chance of coincidental correlation between failed bits and defects increases as the square of tolerance. Analytical and simulation results are presented to illustrate the danger of using the existing kill ratio estimator with too large a tolerance or overly sensitive inspection tool recipes. These same results illustrate the improved performance of the new estimator. Because the number of falsely attributed defects adds up over a number of inspections, a small error in the kill ratio estimator can have a major impact on the yield loss pareto.     

SRAM cell defect isolation methodology by sub micron probing technique

With the complexity of integrated circuitry and the decreasing size of components, usual isolation techniques (SEM inspections, Passive Voltage Contrast…) are not enough to find the defect. This paper presents an accurate methodology using the Sub Micron Probing (SMP) technique applied to a SRAM cell analysis. Indeed the number of non visual defect (NVD) becomes more and more important on the last technologies. In this context, the classical failure analysis must be improved with the electrical methodology. This method consists in using a quantitative electrical I/V characteristic measurement technique at the metallization, vias, and contacts levels during delayering without physical modification and electrical I/V alteration. Moreover, the efficiency of this methodology allows us to guide analysis and to segregate the failure mechanism.     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

Multi-port SRAMs are often implemented using static random access memory (SRAM) due to its fast operation and the ability to support multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust memories and investigating their failure characteristics become critical. In this paper, we study the defects occurring in the multi-port SRAM cells. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of test patterns. Not only have existing models been taken into account in our simulation but also a new fault model, namely, simultaneous deceptive destructive read fault for the multi-port memory is introduced. In addition, we extend our study to the defect tolerant design of memories by proposing a differential current-mode sense amplifier for 3-port SRAM based register file. We examine the fault models of resistive defects within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defects at 4.6× for dual-port read and 5.8× for 3-port read compared to voltage-mode sensing with 0.18 μm manufacturing process technology.     

Open contact analysis of single bit failure in 0.18 μm technology

Single bit failure is the most common failure mode in static random access memory. Although a failing cell can be easily localized with bitmap data, the exact defect location within the failing cell cannot be found immediately, especially when a defect is related to contact. In this paper, a technique of contact-level passive voltage contrast has been proposed to detect such defects for a single bit failure. After an open contact was identified, subsequent transmission electron microscope analysis was performed and it was found that the root cause for the open contact was poly residue.     

Improved SRAM failure diagnosis for process monitoring via current signature analysis

SRAM's are frequently used as monitor circuits for defect related yield, due to the ease of testing and the good correlation to the yield characteristics of logic circuitry. For the identification of the failure/fault type and the nature of the defect causing the failure, measured failbitmaps are mapped onto a failbitmap catalog obtained from defect-fault simulation. Often this mapping is not unique. A given failbitmap can be caused by several faults or defects.In this contribution, the application of current signature analysis is demonstrated for a stand-alone 16kx1 SRAM monitor circuit. It is found that the resolution of the failbitmap-fault-defect catalog can be improved considerably by additional current signature measurements. The interpretation of current measurements is based on simulation of the possible faults contained in the failbitmap catalog under the operating conditions in the current test. There was good agreement between the simulated and measured current values.With the aid of current measurements, more yield learning information is obtained from the process monitoring vehicle. In some cases, the shorted nodes inside a SRAM cell can be determined exactly. This eases the localization of the failure and is of practical importance for the sample preparation in physical failure analysis.     

The device characteristics of missing LDD implantation via nanoprobing techniques for localized failure analysis

In the recent years, localization of subtle defects has required device electrical data. Nanoprobing systems based on scanning electron microscopy (SEM) or atomic force microscopy (AFM) have become a significant tool for device measurement in failure analysis (FA) Labs. Failure Analysts can use electrical characteristics to isolate failure location in the metal–oxide–semiconductor field-effect-transistor (MOSFET). The missing lightly doped drain (LDD) implant is an example of a critical failure mechanism for the MOSFET and cell in the SRAM which is localized using nanoprobing. In this article, device data analysis and theoretical deductions are discussed related to missing LDD doping. Device data is used to propose a full set of characteristic for missing LDD. The simulation from a mature tool is able to support the electrical characteristics. The capability and challenge of the following physical FA to reveal the defect are also discussed.     

Layout analysis as supporting tool for failure localization: Basic principles and case studies

To be able to localize a defect on results obtained by failure analysis tools like emission microscopy or OBIRCH analysis it is necessary to understand the effect of a certain defect on an integrated circuit, as only some defects can directly be pinpointed by these analysis methods. In the majority of cases, only second order effects are visible, e.g., a floating gate will cause a transistor to emit light. In that case, the failure site differs from the point of emission.While the physical principles of common defects are well understood one has also to consider the layout of an integrated circuit. By matching the failure analysis results obtained by emission microscopy or OBIRCH analysis to the layout and schematics of a failing device it is possible estimate the root cause of the failure. Thus, the failure site can be narrowed down, to be finally able to proceed with the physical analysis for root cause determination.This paper will give an overview of physical failures that can occur and their effects on emission and OBIRCH analysis. These failure modes will then be correlated to the layout of a device in order to be able to estimate the root cause of a failure based on analysis techniques like emission microscopy and OBIRCH analysis. Finally, we will present case studies of successful failure localization based on layout analysis.     

In-line yield prediction methodologies using patterned waferinspection information

Due to the advances in in-line inspection technology it is now possible to obtain an early in-line prediction of yield. This paper introduces and compares two new in-line yield prediction methodologies: (1) multilayer critical area method and (2) defect-type-size kill-ratio method. These methods are more accurate than the past and other current approaches used in the semiconductor industry. The first method uses the design layout information along with the in-line defect data, whereas the second method uses the defect and yield data to empirically derive the kill-ratios. We demonstrate our methodologies using data collected in a real wafer fabrication facility at the polysilicon gate (Poly), and the first and second interconnect (Metal 1 and Metal 2) post etch inspection layers. We compare our in-line predictions with the actual yield     

Mechanism of breakdown voltage wavering in power MOSFET induced by silicon crystalline defect

This paper presents the impact of silicon crystalline defects generating mechanism of breakdown voltage degradation on low voltage vertical Power N-MOSFETs, functioning in avalanche mode. The physical defect determination is presented through a full failure analysis: it includes specific sample preparation, electrical characterization using EMMI techniques and physical characterizations using Scanning Electron Microscope, Transmission Electron Microscope and chemical delineation etches. Silicon crystal defects (edge dislocation and stacking fault) are found to be at the origin of the failure. Then, a discussion presents how the failure mechanism impacts the device structure and some possible root cause at the origin of the defect.     

Advanced electrical analysis of embedded memory cells using atomic force probing

To identify the failure cause of embedded memory cells - e.g. SRAM with 6 transistors - it is often necessary to measure the electrical parameters of each transistor. Until now, on integrated circuits with small feature size and pitch, this was only possible using FIB probing pads or SEM probers, but both methods are complex and error-prone. Today Atomic Force Probing (AFP) provides a powerful alternative, allowing fast and non-destructive characterization of single transistors. In this paper the functional principle of the technique is introduced. Three case studies of SRAM, ROM and NVM cells illustrate the successful application of this nano-probing tool.     

Investigation of low temperature SRAM and ROM failures to enable the replacement of cold test insertion by room temperature test

The replacement of cold test insertion by room temperature test is one possibility of cost reduction. Therefore, a screening concept at room temperature was implemented to address the low temperature failures too. Although, a clever screening concept was able to find most of the low temperature failures, some still could not be caught. To enable the cold test replacement the failure mechanisms of these failures had to be understood. This paper describes the analysis of SRAM and ROM cells failing at low temperature, which could not be detected by this screening concept. It includes the electrical characterisation as well as the physical root cause finding.     

In-line defect sampling methodology in yield management: anintegrated framework

In this paper we provide an integrated framework for designing the optimal defect sampling strategy for wafer inspection, which is crucial in yield management of state-of-the-art technologies. We present a comprehensive cost-based methodology which allows us to achieve the trade-off between the cost of inspection and the cost of yield impact of the undetected defects. We illustrate the effectiveness of our methodology using data from several leading fablines across the world. We demonstrate that this work has already caused a significant change in the sampling practices in these fablines especially in the area of defect data preprocessing (declustering), in-line defect based yield prediction, and optimization of wafer inspection equipment allocation     

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH₄) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.     

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

We present a study on the effects of resistive-bridging defects in the SRAM core-cell, considering different industrial technology nodes: 90?nm, 65?nm and 40?nm. We have performed an extensive number of electrical simulations, varying the resistance value of the defects, the supply voltage, the memory size and the temperature. We identified the worst-case conditions maximizing failure occurrence in presence of defects. Results also show that resistive-bridging defects cause malfunction in the defective core-cell, as well as in non-defective core-cells located in the same row and/or column. Moreover, the weak read fault is the fault that is the most likely to occur due to resistive-bridging defects. Finally, the sensitivity of SRAMs to resistive-bridging defects increases with the advance of technology nodes.     

A detailed analysis of CMOS SRAM's with gate oxide short defects

Using a model of gate oxide short defects, previously developed and validated experimentally, we investigate the behavior of CMOS SRAM memories having this defect. Faulty behaviors caused by gate oxide shorts are characterized classifying those that may cause a logic malfunction and those that degrade the memory operation without causing a logic error. Merits of SRAM test algorithms to detect gate oxide shorts are analyzed, identifying which are effective in terms of coverage and test cost     

In-line Inspection Impact on Cycle Time and Yield

The semiconductor industry constantly drives for high yield and low cycle time (CT), while most current manufacturing practices consider them separately. This research investigates and exhibits the relationship between CT and yield as affected by in-line metrology inspections of production lots. Among the various factors that impact the tradeoff between CT and yield, we focus on single operation monitors and investigate their measure rate and scheduling. The research assumes a simplified Production Cell consisting of three operation steps that represent a typical segment in a production line. We compose and apply dynamic policies for metrology inspections via simulation and analytical methods. The aim is to concurrently reduce the CT accumulated and increase the yield achieved due to inspections. Ten inspection policies are compared under nine different operation scenarios. The results of most of the policies present a concave curve of yield versus CT. The curve illustrates that growing inspection rate increases both yield and CT until the yield reaches a maximum and then starts to decline. The cause for the yield decline is longer delay in corrective feedback to an out-of-control production tool due to longer waiting time for inspection. A cost–benefit CT–yield objective function is defined and demonstrates that the newly composed dynamic inspection policies are superior to the commonly used fixed measure rate policy. Future research could relax part of the simplified Production Cell assumptions in order to consider more realistic model structure and scenarios.      

Investigation on marginal failure characteristics and related defects analysed by soft defect localization

Soft defect localization is a well established failure analysis technique for detecting defects causing integrated circuits to marginal fail. First simulations on Shmoo characteristics using a defect model on simple inverter logic have already been presented. However, the influence of a defect on the Shmoo characteristic for more complex circuit structures is not investigated.This paper discuss a correlation of Shmoo results to both, the defect type and failing circuit structure of a SRAM-cell. Soft defect localization has been applied on two examples showing a bridging defect with a SRAM-cell. In both cases the Shmoo characteristics show a strong voltage dependency. The effect of various bridging defects within a SRAM-cell has been simulated and discussed. With these results the Shmoo characteristic should be considered in the analysis for a defect based on soft defect localization.     

Voltage Contrast for Gate-Leak Failures Detected by Electron Beam Inspection

We examine a technique for enhancing the voltage contrast (VC) of a failure analysis (FA) tool, defect review scanning electron microscope (DR-SEM). For an SRAM, we demonstrate a dependence of gate-leak VC on the relative angle (RA) between the direction of beam scanning by the FA tool and the lengthwise direction of the gate electrode. Experimental results show that better VC results are obtained when RA is zero, in other words, a beam's scan-line is parallel with the SRAM gate. We propose a simple qualitative resistor-capacitor model to explain this phenomenon. With the help of this VC enhancement technique of the FA tool, we could tune the electron beam inspection (EBI) recipe to an appropriate condition quicker. The cycle time of EBI recipe tuning was shortened from five to two days. As a result, correct EBI evaluation results of countermeasure experiments led us to a yield enhancement solution within a shorter period of time.