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Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems 相似文献
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Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints 总被引:1,自引:0,他引:1
Guoqing Chen Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(2):161-172
Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect. 相似文献
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Azadpour M.A. Kalkur T.S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(6):1143-1146
Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths. 相似文献
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Ismail Y.I. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(2):195-206
A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale 相似文献
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Joshi A.J. Davis J.A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(8):899-910
In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing technique that harnesses the inherent intraclock period interconnect idleness to implement wire sharing throughout the various hierarchical levels of design. It is illustrated in this paper that the WPM network can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Both, a system level analysis and circuit level verification of this WPM routing are presented in this paper. A multilevel interconnect network design simulator (MINDS) that uses system level interconnect prediction (SLIP) techniques and HSPICE circuit simulations for optimizing the interconnect dimensions has been used to assess the opportunities for application of WPM wire circuits in high performance digital designs. A custom routing example highlights the ease with which the WPM routing technique can be easily incorporated into the existing VLSI systems. In addition, for a 40 million transistor system case study, this system level analysis reveals that the use of a WPM network could result in an almost 20% decrease in the number of metal layers for less than 4% increase in dynamic power with no loss of communication throughput performance. The key virtues of WPM routing are its flexibility, robustness, implementation simplicity and its low overhead requirements. 相似文献
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《Solid-State Circuits, IEEE Journal of》1985,20(5):1005-1011
A 24K-gate CMOS gate array has been developed using triple-level wiring and a hierarchical layout method. A typical delay time is 1.6 ns with a fanout of 3 and a 3-mm metal interconnect length. The master chip was designed to be freely divided into blocks. A previously developed digital signal processor has been realized on the array. The design time was reduced to 25% of the normal design cycle although the chip size is 3.3 times larger than was realized by a handcrafted design. 相似文献
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Varghese J. Butts M. Batcheller J. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1993,1(2):171-174
The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution 相似文献
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El-Moursy M.A. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(3):396-400
Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE. 相似文献
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Sato T. Sylvester D. Yu Cao Chenming Hu 《Solid-State Circuits, IEEE Journal of》2001,36(10):1587-1591
An accurate in situ noise and delay measurement technique that considers interconnect coupling effects is presented. This paper improves upon previous work by proposing (1) a novel accurate peak detector to measure on-chip crosstalk noise, and (2) in situ measurement structure to characterize the dynamic delay effect. A test chip was fabricated using 0.35-μm process and measured results demonstrate the effectiveness of the proposed technique. Noise peak measurements show 40-60 mV (1.8% average) accuracy to simulation results and dynamic delay change curve match well with SPICE. The proposed measurement technique can be used for interconnect model verification and calibration, and has applications to various design automation tools such as noise-aware static timing analysis 相似文献
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This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed 相似文献
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Crosstalk-related issues have become increasingly important with deep submicron downscaling of ICs and wafer scale integration. In today's systems-on-a-chip, the delay through a wire is often greater than the delay through the gate driving it. Furthermore, because of significant parasitic effects, crosstalk between signals on wires can cause major problems. Improved management of the EMI problem is made possible via EDA tools which have the capability of accurately and efficiently modeling electromagnetic interference effects in nanoscale VLSI. However, existing tools are computationally expensive and do not have broad application. The novel methodology proposed in this paper involves topological decomposition of small portions of interconnect (referred to as wirecells) at an extreme level of detail and the creation of parameterized models of these primitive interconnect structures using modular artificial neural networks (MANNs). The technique uses a finite element method program coupled with a circuit simulator and a neural network multi-paradigm prototyping system to produce a library of standard MANN-based wirecell models. It is especially attractive because none of the existing approaches is capable of fully modeling the simultaneous effect on delay and crosstalk of several uncorrelated variables such as interconnect length, width, thickness, separation, metal and insulating medium conductivity and relative permittivity for multiple systems of conductors. The library models derived are used to predict delay noise and crosstalk resulting from interconnect structures embedded in actual analog and digital circuitry 相似文献
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The properties of superconductors are reviewed, and the potential applications of high-temperature superconductors to interconnect technology are examined. Comparison with interconnects composed of normal metals is made. The effect of source and load impedances on both types of interconnect is discussed. Examples are presented in which the use of superconductors can significantly improve digital systems; however, they involve much more than the simple substitution of superconductors for copper. Modeling results show that if all copper interconnects in the ETA-10 liquid nitrogen supercomputer were replaced by superconductors, the computer would not run any faster. It is argued that imaginative use of superconductors will eventually have a major impact on digital systems, nevertheless. Two possibilities are the use of a superconducting ground plane and a high-bandwidth superconducting bus 相似文献
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Guoqing Hui Mikhail Nicholas A. David H. Philippe M. Eby G. 《Integration, the VLSI Journal》2007,40(4):434-446
Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(5):560-571
Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-mum technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16times16 bit multiplier 相似文献