基于NCO的MSK数字调制

在分析了MSK调制信号的特点,给出了一种基于NCO的MSK调制器的全数字实现方式。该方法电路简单、易于实现;可完成MSK信号的正交基带调制和直接数字中频调制。     

基于DDS的π/4-DQPSK调制器设计

π/4-DQPSK调制方式广泛应用于无线通信领域,而全数字合成技术应用于卫星通信和移动通信领域。简要介绍了DDS原理和π/4-DQPSK调制原理。提出了一种新颖的全数字中频π4-DQPSK调制器,该调制器采用DDS技术和先进的FPGA技术。给出了该调制器的硬件实现,并从原理上进行了必要的分析。实验结果表明:提出的设计方案能很好地实现π/4-DQPSK调制,与一般的调制器相比,具有可重新配置、灵活性好、工作更加稳定等优点。     

基于AD9856的多模式通信信号的设计

通过对数字中频正交调制原理的介绍，具体分析了正交数字上变频芯片AD9856的性能特点和多模式信号的算法研究，从而方便容易地实现基于软件无线电技术的全数字调制的各种调制信号。     

一种基于软件无线电的中频接收机实现

介绍了一种基于软件无线电技术的中频数字接收机的实现方案，它主要由数字正交调谐器和数字科斯塔斯环构成，通过配置不同的软件即可实现不同频带、不同调制类型信号的全数字接收。     

基于CPCI总线可重组中频调制器设计与应用

为实现某基带中频调制设备的全数字、低故障率、小型化和可重组目标,采用基于CPCI总线技术和软件重组等设计方法完成了数字化中频调制器的设计。测试和应用结果表明,该调制器各项技术指标满足设计要求、各项功能正常,工作稳定。通过软件重组,可满足现有通用雷达设备的不同调制信号需求。     

全数字正交幅度调制器(QAM)的实现

提出了如何用全数字方法实现QAM调制器。第一部分概述了全数字正交幅度调制器和模拟调制器相比的优点。第二部分论述了数字调制器各个关键部分的实现方法和注意要点,尤其是数字滤波器和数字信号合成技术,正是由于DDS技术应用的普及,全数字调制器的实现变为了现实可行的。第三部分为结论,认为该方法易于大规模集成,性能稳定,功耗低,成本低,而且可以根据需要配置成不同的QAM调制方式,载波频率也可以随意改变。     

一种基于DSP Builder的软件无线电调制器的设计与实现

针对基于FPGA的DSP技术,本文提出了一种基于DSP Builder的软件无线电调制器的设计方法,在DDS的理论基础上,采用DSP Builder软件,设计了具有FSK、PSK、ASK调制功能的数字中频调制器。文中讨论了调制载频的一般理论,并将推导出的相关理论结果运用到仿真调试中,最后在FPGA芯片上验证了调制器的系统功能。     

基于AD6620和ADSP2191的数字中频软件无线电接收系统

提出了一种通用的数字中频软件无线电接收系统的设计及应用方案。该系统可以广泛地应庸于各种中频调制信号的采样与解调。文中介绍了系统的总体结构设计，并分析了系统设计中的几个关键性技术：数据采集技术、数字下变频技术、数字信号处理技术和系统同步互连技术。在软件方面，主要介绍了数字下变频器的参数设置、接收系统的应用软件设计以及系统核心芯片ADSP2191的监控软件设计。     

微波QPSK调制器的性能分析

数字微波直接调制技术有利于减小移动通信设备的体系，降低成本，是目前数字微波通信的一个重要发展的趋势。本文讨论广泛应用的微波ＱＰＳＫ调制器的关键指标，如邻近频道功率，误差矢量幅度等，并介绍调制器诉进展和趋势。     

基于专用数字上变频器的中频调制器

现代通信系统大部分采用数字中频调制技术产生所需要的调制信号,通过数字技术可以减小系统的体积、重量、功耗。其中在复杂的数字中频信号处理系统中,数字上变频器是产生调制信号的一个重要环节。通过对数字中频上变频基本原理和技术特点的研究,采用ADI公司AD9957数字上变频器实现了常见的几种码速率较高的调制波形。     

A VLSI architecture for a high-speed all-digital quadraturemodulator and demodulator for digital radio applications

An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25-μm process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256×256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M-ary PSK and QAM     

A frequency-agile single-chip QAM modulator with beamformingdiversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function     

DOCSIS2.0详解及其ATP测试

在简要介绍DOCSIS发展历史的基础上,重点叙述了DOCSIS2.0上行物理层新增加的S-CDMA调制技术,并且对DOCSIS2.0与DOCSIS1.x在上行物理层所采用调制技术以及不同调制方式和带宽下的频谱效率、最大数据带宽、载噪比门限等方面作了详细分析和比较,最后对基于DOCSIS ATP2.0 Cable Modem的测试作了归纳和总结.     

Full-Duplex DOCSIS/WirelessDOCSIS Fiber–Radio Network Employing Packaged AFPMs as Optical/Electrical Transducers

A hybrid fiber-radio access network architecture for simultaneous wireline and wireless transmissions of data-over-cable service interface specification (DOCSIS) signals is presented. An all-optical harmonic up-conversion technique using a dual-drive Mach-Zehnder modulator provides the downstream optical signal modulated not only at the intermediate frequency in the 600- to 900-MHz band for wireline transmission but also at the up-converted frequency in the 5.45- to 5.75-GHz band for wireless transmission. An InGaAsP/InGaAsP multiple-quantum-well asymmetric Fabry-Perot modulator/detector has been designed, fabricated, and packaged and has been employed in the base station (BS) as an optical/electrical transducer, simultaneously providing the functions of optical intensity modulation and photodetection. At the BS, the DOCSIS signals are recovered at the wireline and wireless frequencies for the respective feeding of a cable access network or a fixed wireless access network in a highly flexible approach. Full-duplex operation has been demonstrated for both access types in an indoor laboratory environment. In a subsequent small-scale field trial, real-life Internet traffic provided by a local community antenna television system operator has been transported over the present hybrid fiber-radio access network architecture, and simultaneous transmission of both DOCSIS and digital television signals has also been performed.     

All-digital reverse modulation architecture based carrier recoveryimplementation for GMSK and compatible FQPSK

A carrier recovery circuit implementation with an all-digital reverse modulation approach for coherent detection in the GSM/GMSK system as well as the GMSK compatible improved efficiency cross-correlated FQPSK system is presented. The proposed carrier recovery implementation utilizes all-digital reverse modulation circuit in a feedback loop to remove the modulated signal from the received intermediate frequency (IF) signal and to estimate the phase error of this carrier signal using a phase-locked loop (PLL). The digital reverse modulation approach avoids the multipliers required in an analog reverse modulation design, so that it can be implemented in a single chip FPGA. Hardware implementation of the coherent detection demonstrates that cross-correlated FQPSK is completely compatible with GMSK in the system performance and the receiver structure for GSM. Experimental performance evaluations show that the proposed carrier recovery circuit provides a Bit Error Rate (BER) performance within 0.3 dB in a non-linearly amplified channel corrupted by additive white Gaussian noise (AWCN) as compared with the simulated performance of the GSM/GMSK system     

宽带数字调制器设计实现

针对现代数字通信系统中广泛使用的宽带数字调制,分析了其矢量合成原理,并采用统一的FPGA硬件平台、算法软件实现、IF/RF矢量调制器来实现。文中给出了实现电路原理,对实际的幅度与相位不平衡给出补偿解决办法。最后给出了多进制相移键控(MPSK)调制器测试数据,其性能优良,可以满足多频段扩跳频数据传输要求。     

一种双耦合双混频中频信号功率反馈电路

在自动电平控制系统中,常用功率反馈电路存在一个主要限制:调幅动态范围受限于电平检波器和相关电路,使其远远低于线性调制器的功率可变范围。文中介绍了一种双耦合双混频中频信号功率反馈电路,使检波器只需检测固定中频信号的功率大小即可反馈调节射频输出信号的功率幅度。经测试,电路射频输入信号在24 GHz变化时,得到的中频信号频率固定不变,等于晶振信号54 MHz。线性调制器的衰减量在031.5 dB变化时,中频信号功率与射频输出信号功率成良好的线性关系,满足预期的设计要求。     

A Novel Alternating and Outphasing Modulator for Wireless Transmitter

This paper describes a novel alternating and outphasing modulator for the generation and amplification of a linear modulation signal. The architecture requires a linear modulation signal to be represented as two outphasing signals with a constant envelope, which are alternating or switching at the input of two nonlinear amplifiers to produce a linear modulation signal. A power combiner can be employed to cancel the mixed components due to the switching. This will minimize the requirements of the output filter, and hence, simplified the design. This new modulation architecture is simple, and hence, is suitable for all-digital integration. The measurement results of the wideband code division multiple access signal are presented and compared with a conventional linear amplification with nonlinear components architecture.      

Analog signal generator for BIST of wideband IF signals bandpass sigma-delta modulator

This paper presents improvements in generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma-delta modulator chip. Via increasing the order of the one-bit bandpass sigma-delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma-delta modulator chip's production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.