An experimental study of backgating effects in GaAs MESFETs

This paper presents the results of a series of experiments concerning the backgating effect in GaAs MESFETs, and high-field current behavior of backgate diode structures. The devices tested were selectively ion-implanted and mesa-etched structures fabricated on semi-insulating (SI) undoped and Cr-doped LEC substrates. These experiments were performed to separate the effects of the substrate bias and the backgate bias and to identify the carrier emission processes using bias variations and optical excitations. The main objective was to determine the effects of surface condition by comparing the behaviors of devices with untreated and nitride-a and Al-deposited SI surfaces. A model for the backgating effect is proposed that involves trapping of electrons near the surface in the backgate structure, and space charge build-up beneath the MESFET channel region by deep-level trapping and free-carrier distribution. The temperature dependence of the backgating high-field current suggests that surface trapping by shallow levels is often significant and this causes the backgating threshold voltage to increase rather rapidly, as the temperature is lowered.     

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current-voltage (I-V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I-V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco^®-TCAD). The proposed model also illustrates the effectiveness of the gate-source distance scaling effect compared to the gate-drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I-V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.     

Bulk traps in silicon-on-sapphire by conductance DLTS

A new deep-level transient spectroscopy (DLTS) technique has been developed for the characterization of deep-level imperfection centers in silicon-on-sapphire (SOS) epitaxial layers, and is based on the use of conductance transients on MOSFET's. Both the distribution of trap levels with energy in the bandgap of silicon and the spatial distribution of levels in the epitaxial film have been obtained. This complete characterization of trapping levels allows process techniques to be developed to control and reduce their concentrations to acceptable levels in SOS technology.     

Mathematical modeling of photoconductor transient response

We present a Photoconductor device model that is based on time-dependent convective/diffusive continuity and transport equations. Electron and hole trapping on deep-level impurities is accounted for by trapping-kinetics rate equations. The coupling between carrier drift and electric field is completed through Poisson's equation. The system of model equations is solved numerically with boundary conditions that represent ideal ohmic contacts. Computed results are presented for different photoconductor lengths and bias voltages with spatially uniform, rectangular light-pulse excitation. Material parameters appropriate for iron-doped indium phosphide are used.     

Gate oxide breakdown statistics in wearout tests of metal-oxide-semiconductor structures

Experimental breakdown data of different MOS structures under different wearout tests support the validity of a new physical approach to the breakdown statistics. This model is based on the idea that the dielectric breakdown is intimately related to the previous degradation of the SiO₂ network, and particularly, to the generation of neutral electron trapping sites. The main properties of the widely used extreme-value statistical distributions are preserved, and the parameters involved have a natural physical interpretation. Only two parameters have been used to build up the model and to fit the experimental: data the minimum area that has to be degraded for the breakdown to be effective, and the critical number of traps that has to be locally generated to trigger the breakdown. Although the analytical calculations have provided excellent results, the Monte Carlo method has been shown to be powerful technique to introduce second-order effects in the sudy of the breakdown statistics.     

Characterization of polysilicon oxides thermally grown anddeposited on the polished polysilicon films

This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Q_bd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide     

Junction breakdown instabilities in deep trench isolationstructures

Junction breakdown voltage instability in a p-n junction formed in bulk silicon adjacent to a deep trench filled with polysilicon was investigated. The structure investigated consists of a 5-μm-deep trench filled with heavily p-doped polysilicon. The trench is open at the bottom and is consequently shorted to the p-substrate. The time-dependent behavior of the walkout or the breakdown voltage instability is similar to that reported for planar p-n junctions terminating on surface oxide. Results suggest that trapping of holes in the trench sidewall dielectric is responsible for this phenomenon. The product of trapping center concentration and capture cross section N σ is estimated to be 90 cm^-1     

Trapping effects and microwave power performance in AlGaN/GaN HEMTs

The dc small-signal, and microwave power output characteristics of AlGaN/GaN HEMTs are presented. A maximum drain current greater than 1 A/mm and a gate-drain breakdown voltage over 80 V have been attained. For a 0.4 μm gate length, an f_T of 30 GHz and an f_max of 70 GHz have been demonstrated. Trapping effects, attributed to surface and buffer layers, and their relationship to microwave power performance are discussed. It is demonstrated that gate lag is related to surface trapping and drain current collapse is associated with the properties of the GaN buffer layer. Through a reduction of these trapping effects, a CW power density of 3.3 W/mm and a pulsed power density of 6.7 W/mm have been achieved at 3.8 GHz     

The TEOS CVD oxide deposited on phosphorus in situ dopedpolysilicon with rapid thermal annealing

A TEOS oxide deposited on the phosphorus in situ doped polysilicon annealed with RTA is shown to have good electrical characteristics such as a high breakdown field (>12 MV/cm), especially for the positive bias, and a large Qbd (26 Coul/cm²). The improvement is believed to be due to the relatively smooth surface of the in situ doped polysilicon and the reduction of the trapping density by RTA     

Deep-level trapping centers in heterostructures for GaN field-effect transistors

Structural and electrophysical properties of heteroepitaxial gallium nitride layers on a sapphire substrate that are grown via the molecular beam epitaxy (MBE) method are studied. The parameters of deep-level trapping centers are determined by the method of the thermostimulated capacitor discharge; the degree of perfection of the film and substrate are determined by the two-crystal X-ray spectrometry method. The following structures are studied: i-GaN (1–2 μm)/GaN 〈Si〉(0.1−0.4 μm) and multilayer structures (Al_0.3Ga_0.7N-GaN-Al_0.3-Ga_0.7N-GaN-Al₂O₃) grown via the MBE method on a sapphire substrate. The effect of reactive ion etching on the energy spectrum of deep-level trapping centers in gallium nitride is studied. The obtained results are used to calculate the energy spectrum of defects in gallium nitride structures. Original Russian Text ? M.S. Andreev, L.E. Velikovskii, T.S. Kitichenko, T.G. Kolesnikova, A.P. Korovin, V.G. Mokerov, S.N. Yakunin, 2007, published in Radiotekhnika i Elektronika, 2007, Vol. 52, No. 7, pp. 880–887.     

High quality interpoly dielectrics deposited on thenitrided-polysilicon for nonvolatile memory devices

High quality interpoly dielectrics have been fabricated by using NH₃ and N₂O nitridation on polysilicon and deposition of tetra-ethyl-ortho-silicate (TEOS) oxide with N₂O annealing. The surface roughness of polysilicon is improved and the value of weak bonds is reduced due to nitrogen incorporation at the interface, which improves the integrity of interpoly dielectrics. The improvements include a higher barrier height, breakdown strength, and charge-to-breakdown, and a lower leakage current and charge trapping rate than counterparts. It is found that this method can simultaneously improve both charge-to-breakdown (up to 20 C/cm² ) and electric breakdown field (up to 17 MV/cm)     

MOS Capacitance-Voltage Characteristics: V. Methods to Enhance the Trapping Capacitance

Low-frequency and High-frequency Capacitance-Voltage (C-V) curves of Silicon Metal-Oxide-linebreak Semiconductor Capacitors, showing electron and hole trapping at shallow-level dopant and deep-level generation-recombination-trapping impurities, are presented to illustrate the enhancement of the giant trapping capacitances by physical means via device and circuit designs, in contrast to chemical means via impurity characteristics previously reported. Enhancement is realized by masking the electron or/and hole storage capacitances to make the trapping capacitances dominant at the terminals. Device and materials properties used in the computed CV curves are selected to illustrate experimental realizations for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.     

Dielectric breakdown characteristics and interface trapping of hafnium oxide films

The reliability and integrity of HfO₂ prepared by direct sputtering of hafnium were studied. By monitoring the current-voltage and current-stressing duration characteristics, we found a significant charge trapping effect in thin film with very short stressing time (<30 s) but the stress-induced trap generation is insignificant. The breakdown characteristics of hafnium gate oxide were also investigated in detail. We found that several soft breakdowns take place before a hard breakdown. Area and stress-voltage effects of the time-dependent dielectric breakdown were observed. Results suggest that the soft and hard breakdowns should have different precursor defects. A two-layer breakdown model of is proposed to explain these observations.     

Effects of laser irradiation of GaAs observed by d.l.t.s.

A Q-switched ruby laser has been used to heat-treat vapourphase-epitaxial (v.p.e.) GaAs. The characteristic A-centre, a deep trapping level at 0.83 eV, is removed using a laser pulse of energy density 0.3 J cm?2. Trapping levels are observed using deep-level transient spectroscopy (d.l.t.s.).     

Thermal Nitridation of Si and SiO/sub 2/ for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO/sub 2/. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO/sub 2/ in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized using I-V, C-V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, and C -V measurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-dowm VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO/sub 2/ and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO/sub 2/-Si interfaces.     

Thermal nitridation of Si and SiO2for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO2. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO2in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized usingI - V, C - V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, andC-Vmeasurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO2and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO2-Si interfaces.     

MOS Capacitance-Voltage Characteristics:V.Methods to Enhance the Trapping Capacitance

正Low-frequency and High-frequency Capacitance-Voltage(C-V) curves of Silicon Metal-Oxide-Semiconductor Capacitors,showing electron and hole trapping at shallow-level dopant and deep-level generation-recombination -trapping impurities,are presented to illustrate the enhancement of the giant trapping capacitances by physical means via device and circuit designs,in contrast to chemical means via impurity characteristics previously reported.Enhancement is realized by masking the electron or/and hole storage capacitances to make the trapping capacitances dominant at the terminals.Device and materials properties used in the computed CV curves are selected to illustrate experimental realizations for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.     

Transport properties of thermal oxide films grown on polycrystalline silicon—Modeling and experiments

A theoretical model considering the effects of Fowler-Nordheim tunneling, image-force lowering, first-order trapping kinetics, impact ionization, and asperity-induced field enhancement has been developed to investigate the ramp-voltage-stressed I-V characteristics of the oxide films thermally grown on the polycrystalline silicon. From the ramp-voltage-stressed I-V measurements, the important physical parameters such as average field-enhancement factor, effective total trapping density, trap capture cross section, recombination capture cross section, and dielectric breakdown field can be extracted. Under a ramp voltage stress, it is shown that the serious asperity effect can lead to a larger leakage current and a weaker dielectric breakdown field, but the serious trapping effect may reduce the leakage current and enlarge the dielectric breakdown field. Moreover, dry O2oxidation at a higher temperature and steam oxidation at a lower temperature can result in a better quality poly-oxide because the asperity-induced field enhancement is weakened and the electron trapping effect is slightly increased. Besides, high-temperature dry O2oxidation can result in a smaller asperity effect as compared with steam oxidation, and the quality of the poly-oxide is deteriorated when the poly-Si substrate is heavily doped because the asperity effect is enhanced.     

Experimental analysis of HEMT behavior under low-temperatureconditions

An experimental analysis of high-electron-mobility transistor (HEMT) behavior under low-temperature conditions is presented. Specific measurements have been performed to investigate the deep-level trapping effects on basic device characteristics such as carrier concentration, electron mobility in the structure, and access resistances. The influence of the collapse phenomenon on the microwave device parameters completes the knowledge of these parasitic effects. Explanation of mechanisms responsible for the anomalous phenomena and means to suppress them are reported. Microwave parameters measurements demonstrate that HEMTs showing no parasitic collapse effects exhibit improved performance at 77 K. Large improvements of current gain cutoff frequency and noise figure are presented     

Trapping, conduction, and dielectric breakdown in Si3N4 films on as-deposition rugged polysilicon

Rugged polysilicon stacked capacitors recently emerged as the storage structures of choice for the manufacture of advanced DRAMs. The authors present the charge-trapping characteristics of such capacitors showing a capacitance increase of more than 50%. It is observed that electron trapping is dominant on rugged structures, whereas hole trapping is observed on smooth structures. Conduction and breakdown properties are also reported. Measurements show that rugged polysilicon capacitors provide the low leakage current, the sharp breakdown distributions, and the trapping characteristics needed for advanced DRAM applications