Controlling substrate currents in junction-isolated ICs

Substrate currents can cause a variety of difficulties ranging from improper operation to catastrophic failure. The effects of substrate currents are characterized and techniques are developed for avoiding problems. Method of optimizing layout to control substrate currents and their effects are discussed. It is shown that these currents are strongly influenced by the properties of the die-attach interface. Fault conditions that can generate destructive hole and electron current densities in the substrate are described, and IC clamp diodes, often required to control these fault conditions, are analyzed. An example gives an appreciation of what must be considered in the design of a practical IC along with the results that might be expected     

Methods for measurement and simulation of weak substrate couplingin high-speed bipolar ICs

On-wafer measurements of very weak substrate coupling in high-speed integrated circuits (ICs) at high frequencies suffer from the direct crosstalk between the input and output RF probes. Two alternative methods to reduce this effect are presented and compared. The first one is based on an advanced deembedding method that eliminates the crosstalk between the RF probes after measurement. The second method utilizes an on-chip broad-band amplifier between the input probe and the substrate test structure. Thus, for a given signal amplitude at the output probe, the amplitude of the input signal can be reduced, resulting in less distortion of the output signal by the crosstalk via the probes. Both methods are compared and verified by measurements up to about 20 GHz even at substrate coupling impedances as high as 0.5 MΩ (corresponding to -80 dB in a 50-Ω system). For this, several substrate test structures (some with the 20-GHz on-chip amplifier) have been designed and fabricated in an SiGe bipolar production technology with 20-Ωcm substrate resistivity. The measurement results agree well with simulation results using our substrate simulator SUSI. As a consequence, the inflexible, expensive, and time-consuming way to determine substrate coupling experimentally is no longer required in future IC designs-not even at very weak coupling and high frequencies. In this work, however, the proposed measuring methods had to be applied to verify the suitability of substrate simulation (with SUSI) under extreme conditions     

Full-wave simulation of electromagnetic coupling effects in RF and mixed-signal ICs using a time-domain finite-element method

This paper describes the computer simulation and modeling of distributed electromagnetic coupling effects in analog and mixed-signal integrated circuits. Distributed electromagnetic coupling effects include magnetic coupling of adjacent interconnects and/or planar spiral inductors, substrate coupling due to stray electric currents in a conductive substrate, and full-wave electromagnetic radiation. These coupling mechanisms are inclusively simulated by solving the full-wave Maxwell's equations using a three-dimensional (3-D) time-domain finite-element method. This simulation approach is quite general and can be used for circuit layouts that include isolation wells, guard rings, and 3-D metallic structures. A state-variable behavioral modeling procedure is used to construct simple linear models that mimic the distributed electromagnetic effects. These state-variable models can easily be incorporated into a VHDL-AMS simulation providing a means to include distributed electromagnetic effects into a circuit simulation.     

Simulation and measurement of supply and substrate noise in mixed-signal ICs

Digital noise in mixed-signal circuits is characterized using a scalable macromodel for substrate noise coupling. The noise coupling obtained through simulations is verified with measured data from a digital noise generator and noise sensitive analog circuits fabricated in the 0.35-/spl mu/m heavily doped CMOS process. The simulations and measurements also demonstrate the effectiveness of including grounded guard rings and separating bulk and supply pins in digital circuits to reduce substrate coupling.     

Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs

A methodology is proposed to characterize through silicon via (TSV) induced noise coupling in three-dimensional (3D) integrated circuits. Different substrate biasing schemes (such as a single substrate contact versus regularly placed substrate contacts) and TSV fabrication methods (such as via-first and via-last) are considered. A compact π model is proposed to efficiently estimate the coupling noise at a victim transistor. Each admittance within the compact model is approximated with a closed-form expression consisting of logarithmic functions. The methodology is validated using the 3D transmission line matrix (TLM) method, demonstrating, on average, 4.8% error. The compact model and the closed-form expressions are utilized to better understand TSV induced noise as a function of multiple parameters such as TSV type, placement of substrate contacts, signal slew rate and voltage swing. The effect of differential TSV signaling is also investigated. Design guidelines are developed based on these results.     

Reliability simulation for analog ICs: Goals,solutions, and challenges

The need for new tools and simulation methodologies to evaluate the impact of all reliability effects in ICs is a critical challenge for the electronic industry. Issues due to process-related variations (also known as spatial variability) are well-known and off-the-shelf simulation methods are available. On the other hand, models and simulation methods for the aging-related problems, which are becoming more important with each technology node, are far less mature, specially for analog ICs. In this sense, transistor wear-out phenomena such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI) cause a time-dependent variability that occurs together with the spatial variability. A fundamental missing piece in the design flow is an efficient and accurate simulation methodology for IC reliability. To this goal, several challenges should be addressed properly: the essential nature of the stochastic behavior of aging (and thus resorting to stochastic models rather than deterministic ones), the correlation between spatial and aging-related variability, and relationship between biasing, stress and aging in analog ICs, among others. This paper discusses some of these challenges in detail.     

Three-dimensional transient thermal simulation: application to delayed short circuit protection in power ICs

Thermal effects may represent a limiting factor in the development of integrated circuits. As the power dissipated by integrated circuits becomes more relevant, the need increases for accurate modeling of the stationary and transient thermal behavior of the die-package structure. An analytical solution of the three-dimensional transient thermal diffusion problem is presented for a two-layer structure, together with a simple computer program for the calculation of the solution. The program, implemented on a minicomputer, is proven to be fast and accurate. The simulation technique is then applied to the design of a new short-circuit protection of a 6A current booster.     

A dynamic synchronization method to realize soft defect localization applied on digital and mixed-mode analog ICs in failure analysis

Failure analysis on advanced logic and mixed-mode analog ICs more and more has to deal with so called ‘soft defects’. In this paper, a dynamic synchronization method is proposed to perform soft defect localization (SDL) technique by Optical Beam Induced Resistance Change (OBIRCH). It is a new and low-cost way to achieve SDL technique by OBIRCH equipment if there is no normal SDL equipment on hand. It extends the application of OBIRCH equipment to a more advanced failure analysis realm. The methodology and system configuration are presented. The experimental results show this dynamic synchronization method is accurate enough to locate a soft defect. Two real cases are studied on a digital IC and a mixed-mode analog IC respectively using this method.     

Laser simulation of ionizing-radiation effects on silicon ICs: The temperature and doping-level dependence of simulation parameters

Experimental results are reported concerning the variation of the linear absorption coefficient with doping level and temperature in silicon subjected to 1.06-μm laser irradiation. They should be useful for accurate evaluation of equivalent dose rates in laser simulations of ionizing-radiation effects on different types of IC. __________ Translated from Mikroelektronika, Vol. 34, No. 6, 2005, pp. 451–454. Original Russian Text Copyright ? 2005 by Gadoev, Skorobogatov.     

EM and substrate coupling in silicon RFICs

An investigation of coupling between inductors and resonators fabricated in silicon substrates is presented and the effects on RF systems and components are discussed. A novel experimental technique to measure inductor and resonator coupling is presented. The experiment is extremely sensitive, fast, accurate, and unique in that no matching, probe de-embedding, or calibration is necessary as the ratio of two on-chip signals is measured to yield the results.     

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the Vdd-Vss admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the Vdd-Vss admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the Vdd-Vss admittances of several test circuits are computed with 2%-3% error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10% maximum error relative to the measurements on a test ASIC fabricated in a 0.18-/spl mu/m CMOS process on a high-ohmic substrate with 18 /spl Omega//spl middot/cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other.     

Minimising mutual coupling in thick substrate microstrip antennaarrays

A new method based on the reaction concept, is used to assess the mutual coupling experienced by two adjacent circular microstrip antennas on a thick substrate. The coupling owing to surface waves is separated out from that due to the direct radiation and the large interference effects exhibited by the former create deep nulls in the overall mutual coupling characteristic: the nulls being dependent on the given choice of substrate geometry and element separation distance. Finally, the application of this coupling minimisation technique to practical arrays having many elements is briefly commented on     

Crosstalk suppression in mixed-mode ICs by the /spl pi/ technology and the future with an SOC integration platform: particle-beam stand (PBS)

A /spl pi/ technology (particle-enhanced isolation, PEI) is proposed to employ penetrating proton beams on the already manufactured mixed-mode (analog-digital) IC wafers (prior to packaging) for the suppression of undesirable substrate coupling. Results indicated that an improvement of 25-30 dB could be achieved by applying a relatively low-fluence proton bombardment on the isolation-intended region in a metal pads pattern. Hall measurements of the irradiated spots were conducted and the associated physics are elaborated on. Issues relevant to the commercial-scale implementation of this technology are also pointed out and discussed. Finally, a /spl pi/-technology-based post-very large scale integration (VLSI) concept: the "particle-beam stand" (PBS) is promoted, which, especially with its design rules pushed to the front end, can potentially serve as the general system-on-a-chip (SOC) integration platform and end most mixed-mode and RF SOC development difficulties.     

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.     

Modeling and analysis of substrate coupling in integrated circuits

This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented     

Method for modelling substrate coupling in large chip designs

The authors present a novel method for modelling substrate noise in large mixed-signal SPICE designs. The approach is very efficient and can be applied to large designs with many digital blocks. An example circuit, which cannot be efficiently analysed with any current method, is used to demonstrate this new method     

Efficient methods for modelling substrate coupling in mixed-signalintegrated circuits

A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits     

混合信号集成电路的衬底耦合噪声分析

本文系统分析了混合信号集成电路的衬底噪声耦合的研究进展.简要分析了衬底噪声的基本机理,及其对混合信号电路的影响,在此基础上分析比较了目前已提出的几种主要的衬底耦合噪声模型.通过分析不同类型衬底内的噪声耦合,介绍了一些电路设计中的去耦方法.最后讨论了衬底耦合噪声研究的发展方向.     

Electromigration: the time bomb in deep-submicron ICs

Electromigration results from the movement of metal ions as current flows through power wires in integrated circuits, causing voids and hillocks in the wires. The voids increase resistance or even cause opens in the wires, while hillocks can cause shorts to adjacent wires. This paper describes how electromigration is a ticking time bomb in IC designs, which can trigger a system failure at some undefined future time. The phenomenon is particularly likely to afflict the thin, tightly spaced power-distribution lines of deep-submicron designs     

Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test

The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-/spl mu/m CMOS technology.