Hot-electron-induced photon energies in n-channel MOSFETs operatingat 77 and 300 K

A detailed experimental study of the spectral distribution of hot-electron-induced photon emission in n-channel MOSFETs is presented. The study significantly improves on previous work by considering energies up to 3.1 eV and different operating temperatures. It is shown that in contrast with previous results, the photon energy distribution is markedly non-Maxwellian, thus suggesting that the same is true for the energy distribution of the channel electrons     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

Miniaturization of Si MOSFET's at 77 K

Micrometer and submicrometer dimension Si MOSFET's have been studied at liquid nitrogen temperature. The emphasis of the study has been on the changes in the minimum channel length required for long-channel behavior Lmindue to cooling. It is found that there is a reduction in Lminwhich is quite considerable in MOSFET's with low-channel doping. We have shown that this effect is due to a shorter lateral depletion width, and therefore longer effective channel length at low temperatures. A drastic decrease in punchthrough current has also been observed.     

50-Å gate-Oxide MOSFET's at 77 K

While hot-carrier-induced degradation is aggravated at cryogenic temperature, a very thin gate-oxide (52-Å) device can still tolerate a 3-V power-supply voltage at 77 K. Hot-carrier-induced degradation may not be the limiting factor in choosing the power-supply voltage and special drain structures may be necessary for very thin gate MOSFET's even at 77 K. However, mobility reduction at high VGis more severe both at lower temperatures and for thinner oxides. Electron mobility appears to be oxide-thickness-dependent at 77 K. The dependence of the electron mobility on the normal field is so strong that it results in unusual I-V characteristics such as negative transconductance at 77 K for an oxide field above 3 MV/cm. The I--V characteristics have been modeled with a mobility dependence on VGSof the form µn ∞ (1 + η(VGS- Vt/Tox)²+ (E/Ec))^-1for 52-Å devices.     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states     

Substrate current measurements in thin SOI MOSFET's at 300 and 77 K

Measurements of impact-ionized hole current in fully depleted SOI (silicon-on-insulator) MOSFETs at room temperature and liquid nitrogen temperature are reported. The measured current exhibits properties similar to those of the substrate current in bulk transistors, except for higher drain biases when the parasitic bipolar in the device is significant. Since the body contact is effective in collecting only a small fraction of the total generated hole current, the body contact cannot be used to eliminate the bipolar action in thin SOI, at least for channel widths on the order of 10 μm     

Scaling silicon MOSFET's for 77 K operation

Using the gradual channel approximation and the velocity-field relationship appropriate to holes in silicon, the static characteristics of Si MOSFETs at 77 K are scaled from those at 300 K to provide similar static characteristics at the two temperatures. Compared to 300 K, the approximate scaling factors for 77 K are 1/4 for voltage, 1/3 for current, 1/12 for static power, 1/16 for dynamic power, and 1/20 for the delay-power product. At 77 K the transconductance is increased by 20% compared to room temperature. Agreement between theory and experiment on p-channel devices is good for channel lengths greater than about 5 μm but the agreement decreases with decreasing channel length. Because the drain voltage required for current saturation decreases with decreasing temperature, circuit operation at supply voltages below 1 V appears feasible     

Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed.     

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Comparison of drain structures in n-channel MOSFET's

Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.     

Hot-electron-induced minority-carrier generation in bipolarjunction transistors

The authors report on the observation and analysis of minority-carrier generation in the collector and the substrate of n-p-n bipolar junction transistors as a result of photons which are generated in the collector-base depletion region. Both the substrate current and the additional leakage current peak at V_BE~0.8 V. In the authors' model of the phenomena, the photons induce the generation of carriers both in the depletion region and in the neutral region. The generated minority carriers in the neutral region diffuse and contribute to the substrate current and the junction leakage current. The contribution of the carriers that are generated in the depletion region is not dominant     

Efficiency of second-harmonic generation in II-VI compound semiconductors at 77 K

The second-harmonic generation efficiency in II-VI compound semiconductors at 77 K under high-field condition has been calculated using a nonlinear analytical approximation for the velocity-field characteristics. It is found that the harmonic generation efficiencies are considerably higher than the corresponding values for elemental semiconductors.     

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V _G-V_T values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1-μm range     

Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

We use the n-channel deep-depletion SOS/MOSFET to measure carrier velocity of electrons in thin SOS films. The data are presented as a function of electric field up to the point where the velocity saturates. We show the consistency of these data across devices of different gate lengths and manufacture operating at different gate voltages. These results lead to the concept of a "universal curve" for the carrier velocity versus electric field relationship which can be applied to the modeling of velocity-saturation effects in n-channel SOS/MOSFET's. We develop a technique for such an application. In addition, by compensating for the effect of surface scattering on mobility, we have been able to show that the velocity versus field relationship at the surface of thin SOS films agrees very closely to that obtained from bulk silicon.     

Threshold-voltage instability of n-channel MOSFET's under bias-temperature aging

New experimental evidence of positive threshold-voltage shift caused by interface state generation under positive bias-temperature (BT) aging is presented. Interface states were estimated for MOSFET's using low-frequency (8-Hz)C-Vmeasurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time(t) and temperature(T) dependence for threshold-voltage shift (deltaV_{T}) is represented experimentally asdeltaV_{T}infin log (t/t_{0}), wheret_{0}^{-1} infin exp (-1.0 eV/kT). The positive VTshift appears faster for MOSFET's fabricated with dry O2oxides as gate insulator than for those with HCI oxides. It is also shown that the VTshift is always larger than the flat-band voltage shift caused by interface state generation under negative BT aging. Generated interface states are distributed in the entire forbidden gap, differing from the case of positive BT aging.     

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3-μm epi film     

Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's

Fully depleted SOI MOSFET's include an inherent parasitic lateral bipolar structure with a floating base. We present here the first complete physically based explanation of the bipolar gain mechanism, and its dependence on bias and technological parameters. A simple, one-dimensional physical model, with no fitting parameters, is constructed, and is shown to agree well with simulations and measurements performed on a new type of SOI MOSFET structure. It is shown that parameters which affect the gain, such as SOI layer thickness, body doping concentration and gate and drain voltages, do so primarily by affecting the concentration of holes in the body region. Thus, current gain falls dramatically with increasing drain voltage due to the associated impact ionization driven increase in the hole concentration. Gummel plots of this parasitic bipolar indicate an apparent ideality factor of 0.5 for the hole current, due to the body hole concentration's dependence on drain voltage     

Fabrication of inversion-type n-channel MOSFET's using cubic-SiC on Si

Inversion-type n-channel MOSFET's of cubic-SiC were successfully fabricated. Cubic-SiC was grown on Si     

Behavior of holes generated by impact ionization in n-channel MOSFET's

The behavior of holes, which are generated mainly by impact ionization, is described with the results obtained from a two-dimensional numerical analysis. The hole density has been found to be large even near the source for shorter channel lengths.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.