A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers

A digital near-end crosstalk (NEXT) canceller merged with an analog equalizer for multi-lane serial-link receivers has been realized in 0.13 $mu{hbox {m}}$ CMOS technology. By applying the proposed sign-sign block least-mean-square (SSB-LMS) circuit, a 5 Gb/s pseudorandom binary sequence (PRBS) of 2 $^{31}-$1 suffered from both the channel loss and NEXT over 10- and 20-inch FR4 traces with the width of 5-mil and the spacing of 7-mil is successfully equalized. The measured bit error rate (BER) is 10$^{-12}$ and the measured maximum peak-to-peak jitter is 49.7 ps. This chip occupies 0.56 $,times,$0.76 $ {hbox {mm}}^{2}$ and the whole circuit including buffers consumes 177 mW from a 1.2 V supply.      

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .      

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2$times$-oversampling phase-tracking CDR, implemented in 90$,$nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of ${pm }{hbox{615~ppm}}$ between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate ${≪} hbox{10}^{-12}$ was verified up to 38 Gb/s using a 2$ ^{7} -$1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90$~$nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 ${hbox{mm}}^{2}$ .      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency contents of the signal. A full-rate bang-bang phase detector with only five latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors. The performance is also improved by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40 Gb/s data passing through a 4 m cable with 10 dB loss at 20 GHz. For an input PRBS of 2 $^{7}-$1, the recovered clock jitter is 0.3 ps$_{rm rms}$ and 4.3 ps$_{rm pp}$. The retimed data exhibits 500 mV $_{rm pp}$ output swing and 9.6 ps$_{rm pp}$ jitter with ${hbox{BER}}≪ 10^{-12}$ . Fabricated in 90 nm CMOS technology, the receiver consumes 115 mW , of which 58 mW is dissipated in the equalizer and 57 mW in the CDR.      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

10-GHz and 20-GHz Channel Spacing High-Resolution AWGs on InP

This letter reports on 10-GHz and 20-GHz channel-spacing arrayed waveguide gratings (AWGs) based on InP technology. The dimensions of the AWGs are 6.8$,times,$8.2 mm$^{2}$ and 5.0$,times,$6.0 mm$^{2}$, respectively, and the devices show crosstalk levels of $-$12 dB for the 10-GHz and $-$17 dB for the 20-GHz AWG without any compensation for the phase errors in the arrayed waveguides. The root-mean-square phase errors for the center arrayed waveguides were characterized by using an optical vector network analyzer, and are 18 $^{circ}$ for the 10-GHz AWG and 28$^{circ}$ for the 10-GHz AWG.      

Temperature-Insensitive Dual-Comb Filter Based on Multimode Interference Ti : LiNbO $_{3}$ Waveguide

A temperature-insensitive dual-comb filter has been demonstrated for the first time by multimode interference based on a Ti : LiNbO$_{3}$ channel waveguide. The phase difference between comb filters was about 180 $^{circ}$. We only observed less than ${pm}$0.125-nm variation of the center wavelength of the filter during temperature change from 20 $^{circ}$C to 50 $^{circ}$C. The measured extinction ratio and channel spacing of the comb filter were about ${-}$25 dB and 3.2 THz, respectively.      

A 10:1 Unequal Wilkinson Power Divider Using Coupled Lines With Two Shorts

A novel unequal Wilkinson power divider is presented. A coupled-line section with two shorts is proposed to realize the high characteristic impedance line, which cannot be implemented by conventional microstrip fabrication technique due to fabrication limitation. The proposed coupled-line structure is compatible with single layer integration and can be easily designed based on an even-odd mode analysis. As a design example, a 10:1 Wilkinson power divider at 2 GHz is fabricated and measured. The measured $-10~{rm dB}$ bandwidth of $S_{11}$ is about 16%, and the isolation $S_{32}$ is better than $-20~{rm dB}$ . The measured amplitude balance between output port 2 and port 3 is between $-10.20~{rm dB}$ and $-9.52~{rm dB}$, and the corresponding phase difference is between 0$^{circ}$ and 4.6$^{circ}$.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

Electrical Properties of Amorphous $hbox{Bi}_{5} hbox{Nb}_{3}hbox{O}_{15}$ Thin Film for RF MIM Capacitors

Amorphous $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}(hbox{B}_{5} hbox{N}_{3})$ film grown at 300 $^{circ}hbox{C}$ showed a high-$k$ value of 71 at 100 kHz, and similar $k$ value was observed at 0.5–5.0 GHz. The 80-nm-thick film exhibited a high capacitance density of 7.8 fF/$muhbox{m}^{2}$ and a low dissipation factor of 0.95% at 100 kHz with a low leakage-current density of 1.23 nA/ $hbox{cm}^{2}$ at 1 V. The quadratic and linear voltage coefficient of capacitances of the $hbox{B}_{5}hbox{N}_{3}$ film were 438 ppm/$hbox{V}^{2}$ and 456 ppm/V, respectively, with a low temperature coefficient of capacitance of 309 ppm/$^{circ}hbox{C}$ at 100 kHz. These results confirmed the potential of the amorphous $hbox{B}_{5}hbox{N}_{3}$ film as a good candidate material for a high-performance metal–insulator–metal capacitors.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

Operation of a 25-Gb/s Direct Modulation Ridge Waveguide MQW-DFB Laser up to 85 $^{circ}$ C

We demonstrated a 25-Gb/s direct modulation up to 85 $^{circ}$C with a 1.3- $mu$m InGaAlAs ridge-waveguide multiple-quantum-well distributed-feedback laser. The dependence of the relaxation oscillation frequency on current was 3.3 GHz/mA$^{1 / 2}$, and this is the highest value ever reported for 200-$mu$m-long lasers in the 1.3-$mu$m wavelength region. The $alpha$ parameter was around 2.7 at 25 $^{circ}$C, and an error-free operation after a 10-km single-mode fiber transmission was obtained up to 85 $^{circ}$C.      

Evaluation of High-Temperature Absorption Coefficients of Ionized Gas Plasmas in Optical Fibers

The large absorption coefficient $alpha$ of a fiber core at high temperatures is closely related to the generation of a fiber fuse. When silica glass is heated to a temperature above 4500 K, it forms Si $^{+}$ and O $^{+}$ ions and electrons in the ionized gas plasma state. We estimate the $alpha$ value for the plasma in the fiber core at high temperatures. $alpha$ begins to increase at 3500 K, then increases rapidly with increasing temperature above 4000 K, reaching a value of $1times 10^{7}$ m$^{-1}$ at 6000 K. This value is about 300 times that necessary for initiating a fiber fuse.      

A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement

Recent trends in the development of integrated silicon frequency sources are discussed. Within that context, a 25-MHz self-referenced solid-state frequency source is presented and demonstrated where measured performance makes it suitable for replacement of crystal oscillators (XOs) in data interface applications. The frequency source is referenced to a frequency-trimmed and temperature-compensated 800-MHz free-running $LC$ oscillator (LCO) that is implemented in a standard logic CMOS process and with no specialized analog process options. Mechanisms giving rise to frequency drift in integrated LCOs are discussed and supported by analytical expressions. Design objectives and a compensation technique are presented where several implementation challenges are uncovered. Fabricated in a 0.25-$mu$m 1P5M CMOS process, and with no external components, the prototype frequency source dissipates 59.4 mW while maintaining ${pm} 152$ ppm frequency inaccuracy over process, ${pm} 10hbox{%}$ variation in the power supply voltage, and from ${-}$ 10 $^{circ}$ C to 80 $^{circ}$ C. Variation against other environmental factors is also presented. Nominal period jitter and power-on start-up latency are 2.75 ps$_{rm rms}$ and 268 $mu$s, respectively. These performance metrics are compared with an XO at the same frequency.      

Operation of Pt/AlGaN/GaN-Heterojunction Field-Effect-Transistor Hydrogen Sensors With Low Detection Limit and High Sensitivity

To enhance the device sensitivity and detection limit, a gate bias is applied to the catalytic metal of AlGaN/GaN-heterojunction field-effect-transistor (HFET) hydrogen sensors to control the carrier concentration in the channel at operation. The sensors exhibit a good sensitivity at temperatures up to 800 $^{circ}hbox{C}$ and a detection limit of 10-ppb $ hbox{H}_{2}$ in $hbox{N}_{2}$. The dependence of the device sensitivity on gate and drain biases has been investigated. The sensitivity peaks at the gate bias of threshold voltage and the drain bias of knee voltage in sensing gas. At high temperatures and $hbox{H}_{2}$ concentrations, specifically from 300 $^{circ}hbox{C}$ and 1000-ppm $hbox{H}_{2}/hbox{N}_{2}$, respectively, the sensitivity of HFETs at $V_{rm gs} = -hbox{3.5} hbox{V}$ and $V_{rm ds} = hbox{1} hbox{V}$ is more than three orders higher than their sensitivity at $V_{rm gs} = hbox{0} hbox{V}$ and the sensitivity of Schottky diodes.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

Quasi Microstrip Leaky-Wave Antenna With a Two-Dimensional Beam-Scanning Capability

A quasi microstrip leaky-wave antenna (QMLWA) with a two-dimensional (2-D) beam-scanning capability is presented in this paper. QMLWA consists of two half-width microstrip leaky-wave antennas with a phase-shifter. This new type of microstrip leaky-wave antenna has the advantages of reducing size, 2-D beam-scanning and suppressing back lobes. The main lobe scanning in H-plane ($y-z$ plane) is achieved through varying the operating frequency. When the operating frequency increases from 4.4–6 GHz, the main lobe scans from 84 $^{circ}$ to 26 $^{circ}$ in H-plane continuously. The main lobe steers in quasi-E-plane with varying the phase difference between two half-width microstrip leaky-wave antennas. The lobe scans from 78$^{circ}$ to 103$^{circ}$ in quasi-E-plane at 5.4 GHz. The experimental results show this short QMLWA (about 2 wavelengths) leaks power effectively. The back lobe in H-plane of QMLWA is suppressed 13 dB as compared with the conventional whole width MLWA at 5.4 GHz as example. The H-plane radiation characteristics of QMLWA are mainly determined by the width $s$ of half-width MLWA and the distance $D$ between two half-width MLWA together. This size-reduced QMLWA is useful in the automotive radar system and air traffic control.      

A 300 nW, 15 ppm/$^{circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 $mu$m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745$~$mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/ $^{circ}$C at best and 15 ppm/$^{circ}$C on average, in a range from ${-}$ 20 to 80$^{circ}$ C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4–3 V, and the power supply rejection ratio (PSRR) was ${-}$45 dB at 100 Hz. The power dissipation was 0.3 $mu$W at 80$^{circ}$C. The chip area was 0.05 mm$^2$ . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.