Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

CAD tools for the synthesis and layout of SC filters and networks

This paper describes two programs for the synthesis and layout generation of SC filters and networks. The first part of the paper describes a technology-independent synthesis and optimization program for SC filters. The program allows for the exact synthesis of cascaded SC biquad and SC ladder filters. Two performance measures related to sensitivity and noise are employed to estimate the performance of the synthesized circuits and to select optimum realizations. The same measures are used in a novel capacitance assignment procedure. The second part of the paper describes a flexible SC layout generator, which can be adapted to various design rules and floorplans by means of a technology file. Area efficient layout is generated by placing individual circuit elements rather than building blocks. Crosstalk between conductors is minimized by a router that distinguishes between different kinds of nodes.1. The scaling of the biquad circuit is dependent on the position of the biquad in the cascade.2. This may not seem to be overly important, since high-pass-type filters do not occur that often in practical applications. If one considers, however, that SCSYN is to be used as a general filter synthesis program, thenevery filter must be automatically realizable. In such an environment, a CAD program that can design all but one type of filter is either quite useless or very limited indeed.3. Note that an SC filter, in contrast to a digital filter, may contain delay-free loops.     

FEN filter design using tantalum and silicon integrated circuits

An economical approach to integrated active RC filter design is described. Complex filter networks are broken down into a series of cascadable second-order filter sections consisting of tantalum thin-film RC networks and semiconductor integrated operational amplifiers. Two building blocks are available for any desired frequency within a decade and for any desired filter function (e.g., low-pass, high-pass, band-pass, band-reject, all-pass, etc.). One building block is for low Q realizations and contains one amplifier; the other is for high Q realizations and contains two. The considerable versatility of this approach is obtained by 1) a network synthesis approach based on decomposing a given second-order function into a low Q asymptotic approximation of this function in cascade with an active frequency emphasizing network and 2) by the characteristics of tantalum and silicon integrated circuits.     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

Physical design of testable VLSI: techniques and experiments

It is shown that the layout of VLSI circuits can affect testability and in some cases reduce the number of faults likely in a design, easing test generation. A method for analyzing circuits at the symbolic layout level and enhancing testability using local transformations is presented. To demonstrate the application of the technique a set of CMOS standard cells was redesigned. The standard cells are used in the MIS synthesis system, allowing the designer to modify interactively designs to perform tradeoff analysis on testable designs. To show the usefulness of the technique, an experiment was performed: example circuits were synthesized, and test vectors were generated and then used in a transistor-level fault simulator. It was found that the modified designs have significantly higher fault coverage than unmodified designs. A strategy for the synthesis of easily testable combinational random logic circuits is presented     

Novel multiple function analog filter structures and a dual-mode multifunction filter

This paper reports three multi-function filters each of which realizes at least three basic functions without any external passive elements. Depending on the circuit, from one to four operational transconductance amplifiers (OTAs), and two operational amplifiers (OPAMPs) are employed. All three circuits are transimpedance-mode circuits; one of them can also operate as a current-mode filter. Therefore this filter represents a dual-mode, multifunction filter. The presented theory is verified with macro models in simulation program with integrated circuit emphasis (SPICE) simulations and post layout simulations, which are carried out with parasitics extracted from the layouts of the filter chips.     

2 to 23 GHz BiFET low noise amplifier design flow and implementations in 0.25 μm SiGe BiCMOS technology

Two BiFET LNAs are here reported, implemented in a 0.25 μm BiCMOS technology from ST Microelectronics. First of them, dedicated to WCDMA standard, depicts a 15.5 and 2.85 dB, S₂₁ and noise figure (NF), respectively, under 2 mA current consumption. The second realization operates at 23 GHz for Mini-Link application. It provides a 14 dB gain and 7 dB at 22 GHz NF for an 8.2 mA current consumption under 2.5 V. Both circuits were designed according to a design flow, here depicted, based on input matching, NF and gain optimisation. A large part of the article also deals with high frequency layout considerations. Indeed useful techniques dedicated to integrated microstrip waveguides and RF inter-connections are proposed based on 3D electromagnetic field simulations.     

Fully integrated CMOS UWB pulse generator

The design of a fully integrated CMOS ultra-wideband (UWB) pulse generator for the 3.1-10.6 GHz frequency band is presented. The pulse generation is based on the filter impulse response technique. With such a technique, the pulse matches the FCC mask with no need for an expensive external filter. The layout of this circuit in a 0.13 mum CMOS technology shows a surface area of less than 0.57 mm² and a power consumption of around 20 mW     

一种计算集成VDMOS管导通电阻的3D解析模型

功率集成电路要在同一块芯片上集成功率器件和低压电路。由于集成VDMOS器件的漏极也要从芯片表面引出,与常规的VDMOS器件相比其导通电阻计算有很大的差别。文中针对三维立体结构中器件的源胞个数和排列以及芯片表面漏极布局的不同,给出了一种新的3D解析模型,可有效地计算集成VDMOS的导通电阻值,并可预测限定面积下达到最小有效导通电阻值所需要的源胞个数和排列布局。     

OTA-C biquad-based filter silicon compiler

An integrated software system that facilitates the design, and integrated-circuit layout of continuous-time OTA-C filter biaquad-based structures with typical cutoff frequenceis for a 3µm technology in the 500 kHz-8 MHz range is described. The proposed integrated software system consists of three separate software modules written in the C language for the Apollo workstation (DN3000). The first module is a general filter approximation package. This program can approximate conventional magnitude, arbitrary magnitude, arbitrary group delay equalizer, arbitrary magnitude with group delay specifications. The second module aides in the synthesis of the biquad-based OTA-C filter structures. This module is unique in that the C code has the rule-based language CLIPS embedded within the code, and takes into account OTA-C filter nonidealities. An expert system using CLIPS was developed to select an appropriate OTA-C filter structure based on the nonidealities of the structures. After the filter structure has been chosen, the program will guide the user in the calculation of the capacitor values. These calculations are based on the nonidealities of the OTAs included in the standard cell library for layout, in addition the design of special purpose OTA as another alternative is also considered. Furthermore, the program will develop the necessary input files for the layout generator. The final module is a modified version of AIDE2, a standard cell layout generator for switched-capacitor circuits. The input files to the modified AIDE2 is a C language program that describes the circuit (i.e., standard cells and their netlist). The output file is a CALTECH Intermediate Format (CIF) file that is required for fabrication.1. The first version of FIESTA [22] was written in basic for personal computers and it is a primitive (and reduced) version of the second version here discussed.2. Not yet implemented in current version of FIESTA.3. In figure 3 the input currentsI _{in 1},I _{in 2},I _{in 3} can be implemented using OTAs.4. The OTA-C filter can be tuned using the tail currents of the OTAs. Therefore, the capacitors do not need to be any exact value.     

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies

Considering the potential risks of piracy and malicious manipulation of complex integrated circuits using worldwide distributed manufacturing sites, an effective and efficient reverse engineering process allows the verification of the physical layout against the reference design. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the recovery of the design from a physical device. Using this reverse engineering process on a physical chip layout, a circuit graph based partitioning of circuit blocks and an Elliptic Curve Cryptography (ECC) module identification will be performed. For the first time, the error between the generated layout and the design GDS layout will be compared quantitatively as a figure of merit (FoM). We propose a new classification of malicious manipulations based on their layout impact.     

Strategies for design automation of high speed digital filters

Optimization techniques for DSP circuits are described based on the design experience with a number of high-speed digital filter chips. These designs show that efficient high speed digital filter designs can be achieved using several optimizations at the architecture, circuit, and layout level. The problems of automating these optimizations in a general DSP synthesis environment are discussed, and possible CAD solutions are proposed.     

Accurate circuit model of interdigital capacitor and itsapplication to design of new quasi-lumped miniaturized filters withsuppression of harmonic resonance

A general-purpose circuit model of a microstrip interdigital capacitor (IDC) is presented in this paper for use in the design of new quasi-lumped miniaturized filters. This computer-aided-design-oriented model is developed as a versatile admittance π-network with the short-open calibration technique that we have recently proposed for accurate parameter extraction of a circuit from its physical layout. This technique is self-contained in our method of moments, which accounts for frequency dispersion and fringing effects. A J-inverter topology is further conceived to explicitly formulate the coupling behavior of three types of IDC's. This model provides a unique way for the IDC-related circuit synthesis and optimization based on the accurate equivalent-circuit network extracted from the field theory algorithm. It is validated theoretically and experimentally through an example of a line resonator connected with two IDC's. The proposed scheme is used in the design and optimization of new low-loss miniaturized quasilumped integrated circuits, namely, two types of three-pole direct-coupled bandpass filters. Our measured and predicted results show interesting features of the proposed filter structure such as size reduction and suppression of harmonic resonance if the line resonator is attached by series-connected equivalent inductance     

A metal-oriented layout structure for CMOS logic

A design method is described for the realization of large digital modules of random logic for custom integrated circuits in CMOS technology. The layout structure is based on the gate matrix concept with a metal orientation instead of a polysilicon orientation. The symbolic layout is obtained by using 11 different microcells with simple assembly rules. It is derived from the functional specifications of the circuit (Karnaugh maps) using a very simple and attractive method. A CAD program for translating the symbolic layout into a geometrical one is described. It works by assembling geometrical microcells. The advantages and disadvantages of the metal-oriented structure are analyzed through examples of industrial designs. The technique is not suitable for fast circuits. However, it results in an improvement of productivity by a factor of about four and a packing density for large modules which is at least comparable with that of nonoriented hand layouts.     

CMOS单元版图生成中的晶体管布局算法

本文提出了一个基于模拟退火技术的CMOS标准(库)单元版图生成中的单元内晶体管布局算法，在满足高度约束的前提下同时优化单元版图的面积和时延，可处理不局限于静态串并联结构的电路，考虑大尺寸管子折叠等因素，最终生成二维样式标准单元版图。     

Synthesis of optical circuits using binary decision diagrams

The advances in silicon photonics motivated the consideration of optical circuits as a new and emerging circuit technology. In particular for ultra-fast interconnects, optical circuits may provide a suitable alternative since it avoids the conversion of signals from the optical to the electrical domain. Accordingly, design automation of this kind of circuits received significant attention. In this work, we consider synthesis of optical circuits based on Binary Decision Diagrams (BDDs). Although BDDs allow for a direct mapping of the function representation to an optical circuit (and, hence, a scalable synthesis), they have their shortcomings with respect to dedicated cost metrics. In this work, we investigate this issue and provide an overview of the BDD-based synthesis schemes which are available thus far. Afterwards, we propose new solutions based on a dedicated BDD optimization which aim for addressing the known shortcomings. Experimental results confirm the benefits of the proposed approach.     

Synthesis of coherent two-port optical delay-line circuit with ringwaveguides

A method has already been reported by the author and others for synthesizing coherent two-port lattice-form optical delay-line circuits which have the same filter characteristics as finite impulse response (FIR) digital filters. This paper proposes a two-port circuit configuration with ring waveguides which can realize the same filter characteristics as infinite impulse response (IIR) digital filters. It also describes a synthesis method for realizing arbitrary IIR filter characteristics with the circuit configuration. This method is based on scattering matrix factorization. Some synthesis examples are demonstrated including an elliptic filter, a Butterworth filter, an optical filter with maximally flat group-delay characteristics, a group-delay dispersion equalizer, and a multichannel selector