AlGaN/GaN Schottky barrier diodes on silicon substrates with various Fe doping concentrations in the buffer layers

This study demonstrated AlGaN/GaN Schottky barrier diodes (SBDs) for use in high-frequency, high-power, and high-temperature electronics applications. Four structures with various Fe doping concentrations in the buffer layers were investigated to suppress the leakage current and improve the breakdown voltage. The fabricated SBD with an Fe-doped AlGaN buffer layer of 8 × 10¹⁷ cm^− 3 realized the highest on-resistance (R_ON) and turn-on voltage (V_ON) because of the memory effect of Fe diffusion. The optimal device was the SBD with an Fe-doped buffer layer of 7 × 10¹⁷ cm^− 3, which exhibited a R_ON of 31.6 mΩ-cm², a V_ON of 1.2 V, a breakdown voltage of 803 V, and a buffer breakdown voltage of 758 V. Additionally, the low-frequency noise decreased when the Fe doping concentration in the buffer layer was increased. This was because the electron density in the channel exhibited the same trend as that of the Fe doping concentration in the buffer layer.     

Numerical analysis on the LDMOS with a double epi-layer and trench electrodes

We proposed a new lateral double-diffused MOS (LDMOS) structure employing a double p/n epitaxial layer, which is formed on p⁻ substrates. Trenched gate and drain are also employed to obtain uniform and high drift current density. The breakdown voltage and the specific on-resistance of the proposed LDMOS are numerically calculated by using a two-dimensional (2D) device simulator, Medici. The n⁻ drift region and upper p⁻ region of the proposed LDMOS are fully depleted in off-states employing the RESURF technique. The simulation results show that the breakdown voltage is 142 V and specific on-resistance is 183 mΩ mm² when the cell pitch of the LDMOS is 7.5 μm. The proposed LDMOS shows better trade-off characteristics than the previous results.     

A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P⁺ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P⁺ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P⁺ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84 V of the conventional LDMOS on 1 µm silicon layer and 2 µm buried oxide layer. Also, effective values of doping, length, and depth of P⁺ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.     

Characterization of HgCdTe MWIR Back-Illuminated Electron-Initiated Avalanche Photodiodes

This article reports new characterization data for large-area (250 μm ×  250 μm) back-illuminated planar n-on-p HgCdTe electron-initiated avalanche photodiodes (e-APDs). These e-APDs were fabricated in p-type HgCdTe films grown by liquid-phase epitaxy (LPE) on CdZnTe substrates. We previously reported that these arrays exhibit gain that increases exponentially with reverse bias voltage, with gain-versus-bias curves that are quite uniform from element to element, and with a maximum gain of 648 at −11.7 V at 160 K for a cutoff wavelength of 4.06 μm. Here we report new data on these planar e-APDs. Data from a third LPE film with a longer cutoff wavelength (4.29 μm at 160 K) supports the exponential dependence of gain on cutoff wavelength, for the same bias voltage, that we reported for the first two films (with cutoffs of 3.54 μm and 4.06 μm at 160 K), in agreement with Beck’s empirical model for gain versus voltage and cutoff wavelength in HgCdTe e-APDs. Our lowest gain-normalized current density at 80 K and zero field-of-view is 0.3 μA/cm² at −10.0 V for a cutoff of 4.23 μm at 80 K. We report data for the temperature dependence of gain over 80 K to 200 K. We report, for the first time, the dependence of measured gain on junction area for widely spaced circular diodes with radii of 20 μm to 175 μm. We interpret the variation of measured gain with junction area in terms of an edge-enhanced electric field, and fit the data with a two-gain model having a lower interior gain and a higher edge gain. We report data for the excess noise factor F(M) near unity for gains up to 150 at 196 K. We describe the abrupt breakdown phenomenon seen in most of our devices at high reverse bias.     

Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature

In this paper, we have investigated the electrical characteristics of power lateral double-diffused MOSFETs (LDMOSFETs) having different gate lengths (2.1–3 μm) and drift lengths (6.6–12.6 μm) in the temperature range 100–500 K. The results of this study indicate that gate length and drift region length have a great effect on electrical characteristics, but they have little effect on temperature dependence. The specific on-resistance and the off-state breakdown voltage increase with temperature. The result shows that the specific on-resistance increases exponentially with the exponent 2.2 and, by contrast, the off-state breakdown voltage increases linearly with a slope of 100 mV/K (drift region concentration of measured device: 2×10¹⁵ cm⁻³). As a result, R_on/BV, known for a figure of merit of power device, increases with temperature.     

Ultrahigh-power picosecond current switching by a silicon sharpener based on successive breakdown of structures

Ultrafast current switching by a silicon sharpener based on successive breakdown of structures has been experimentally implemented and theoretically studied. A voltage pulse with an amplitude of 180 kV and a rise time of 400 ps was applied to a semiconductor device containing 44 series-connected diode structures positioned in a 50-Ω transmission line. After device switching, pulses with an amplitude of 150 kV and a rise time of 100 ps were obtained in the transmission line. Numerical simulation showed that the electric field near the p-n junction reaches the Zener breakdown threshold (∼10⁶ V/cm) at an input voltage rise rate of more than 4 × 10¹³ V/s per structure achieved in the experiment, even when the diode structure contains technological impurities with deep ionization levels and a concentration of 10¹¹ cm⁻³.     

Parylene based bilayer flexible gate dielectric layer for top-gated organic field-effect transistors

In this paper, we report on a bilayer insulating film based on parylene-c for gate dielectric layers in top-gate/bottom-contact inkjet-printed organic field-effect transistors (OFETs) with indacenodithiophene-co-benzothiadiazole (IDTBT) and poly([N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bitthiophene)) (P(NDI2OD-T2)) as with p- and n-channel semiconductors. The thin parylene-c film (t = 210 nm) show large gate leakage density (2.52 nA/cm² at 25 V) and low breakdown voltage (2.2 MV/cm). In addition, a degraded field-effect mobility (μ) was observed in printed IDTBT and P(NDI2OD-T2) OFETs with the parylene-c single-layered dielectric. X-ray photoelectron spectroscopy (XPS) analysis reveals that the degradation of μ is due to unwanted chemical interaction between parylene-c and the conjugated polymer surface during the parylene-c deposition process. By inserting 50-nm thick poly(methyl-methacrylate) (PMMA) and polystyrene (PS) layer in-between the parylene-c and conjugated polymer film, highly improved gate leakage density and breakdown voltage are achieved. The printed IDTBT and P(NDI2OD-T2) OFETs with a bilayer dielectric compose of parylene-c and PMMA and PS show significantly improved hole and electron μ of 0.47 cm²/Vs and 0.13 cm²/Vs, respectively, and better operation stability. In addition, we demonstrate inkjet-printed polymer complementary inverter with a high voltage gain of 25.7 by applying a PS/parylene-c bilayer dielectric.     

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm² and 3.9 V, respectively.     

Tunable Coplanar Waveguide Phase Shifter Using Ba<Subscript>x</Subscript>Sr<Subscript>1−x</Subscript>TiO<Subscript>3</Subscript> Thin Films on LaAlO<Subscript>3</Subscript> Substrates

A kind of distributed coplanar waveguide (CPW) phase shifter based on LaAlO₃ substrates is designed and fabricated in this paper. The Ba_0.4Sr_0.6TiO₃ (BST) thin films employed in the circuits are deposited by RF magnetron sputtering, and then annealed at 800°C for 30 min in air. The dielectric tunability, loss tangent of the BST films are respectively 43.7% and 0.017 at 100 kHz and 30 V, the leakage current is approximately 1 × 10⁻⁹A/cm² at zero bias voltage. The CPW phase-shifter designed is subsequently fabricated in order to obtain a 360° phase shift at 30 GHz with a moderate bias voltage. The maximal phase shift is 372° at 22.5 GHz with a bias voltage of 40 V.     

Fabrication of Metal–Oxide–Diamond Field-Effect Transistors with Submicron-Sized Gate Length on Boron-Doped (111) H-Terminated Surfaces Using Electron Beam Evaporated SiO<Subscript>2</Subscript> and Al<Subscript>2</Subscript>O<Subscript>3</Subscript>

A H-terminated surface conductive layer of B-doped diamond on a (111) surface was used to fabricate a metal–oxide–semiconductor field-effect transistor (MOSFET) using an electron beam evaporated SiO₂ or Al₂O₃ gate insulator and a Cu-metal stacked gate. When the bulk carrier concentration was approximately 10¹⁵/cm³ and the B-doped diamond layer was 1.5 μm thick, the surface carrier mobility of the H-terminated surface on the (111) diamond before FET processing was 35 cm²/Vs and the surface carrier concentration was 1.5 × 10¹³/cm². For the SiO₂ gate (0.76 μm long and 50 μm wide), the maximum measured drain current at a gate voltage of −3.0 V was −75 mA/mm and the maximum transconductance was 24 mS/mm, and for the Al₂O₃ gate (0.64 μm long and 50 μm wide), these features were −86 mA/mm and 15 mS/mm, respectively. These values are among the highest reported direct-current (DC) characteristics for a diamond homoepitaxial (111) MOSFET.     

Electrical Properties of Organic–Inorganic Semiconductor Device Based on Rhodamine-101

Rhodamine-101 (Rh101) thin films on n-type Si substrates have been formed by means of evaporation, thus Sn/Rh101/n-Si heterojunctions have been fabricated. The Sn/Rh101/n-Si devices are rectifying. The optical energy gaps have been determined from the absorption spectra in the wavelength range of 400 nm to 700 nm. Rh101 has been characterized by direct optical absorption with an optical edge at 2.05 ± 0.05 eV and by indirect optical absorption with␣an optical edge at 1.80 ± 0.05 eV. It was demonstrated that trap-charge-limited current is the dominant transport mechanism at large forward bias. A␣mobility value of μ = 7.31 × 10⁻⁶ cm² V⁻¹ s⁻¹ for Rh101 has been obtained from the forward-bias current–voltage characteristics.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Growth and characterization of indium oxide diodes prepared by reactive magnetron sputtering

The electrical properties of Cr/Pt/Au and Ni/Au ohmic contacts with unintentionally doped In₂O₃ (U-In₂O₃) film and zinc-doped In₂O₃ (In₂O₃:Zn) prepared by reactive magnetron sputtering deposition are described. The lowest specific contact resistance of Cr/Pt/Au and Ni/Au is 2.94 × 10⁻⁶ and 1.49 × 10⁻² Ω-cm², respectively, as determined by the transmission line model (TLM) after heat treatment at 300 °C by thermal annealing for 10 min in nitrogen ambient. The indium oxide diodes have an ideality factor of 1.1 and a soft breakdown voltage of 5 V. The reverse leakage current prior to breakdown is around 10⁻⁵ A.     

Characteristics of Ni/SiC Schottky diodes grown by ICP-CVD

A Ni/SiC Schottky diode was fabricated with an α-SiC thin film grown by the inductively coupled plasma chemical vapor deposition, ICP-CVD method on a (1 1 1) Si wafer. The α-SiC film was grown on a carbonized Si layer that the Si surface had been chemically converted to a very thin SiC layer by the ICP-CVD method at 700 °C. To reduce defects between the Si and α-SiC, the surface of the Si wafer is slightly carbonized. The film characteristics of α-SiC were investigated by employing TEM and FT-IR. A sputtered Ni thin film was used for the anode metal. The boundary status of the Ni/SiC contact was investigated by AES as a function of annealing temperature. It is shown that the ohmic contact could be acquired below 1000 °C annealing temperature. The forward voltage drop of the Ni/α-SiC Schottky diode is 1.0 V at 100 A/cm². The breakdown voltage is 545 V which is five times larger than the ideal breakdown voltage of a silicon device. Also, the dependence of barrier height on temperature was observed.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Field-Emission Performance of Wormhole-Like Mesoporous Tungsten Oxide Nanowires

We prepared wormhole-like mesoporous tungsten oxide nanowires on a Cu-tape/Si substrate, and explored the field-emission performances. The wormhole-like mesoporous tungsten oxide nanowires of 20 nm diameter exhibited excellent field-emission properties with extremely low turn-on and threshold fields (emission current density of 10 μA/cm² and 10 mA/cm²) of 0.083 V/μm and 1.75 V/μm, respectively, as well as current stability of about 1400 μA/cm² at a fixed field of 0.67 V/μm. This approach provides an efficient methodology for fabricating a field emitter that is expected to work at low voltage and can be used in field-emission displays.     

Development of embedded capacitor with bismuth-based pyrochlore thin films at low temperatures for printed circuit board applications

Bi₂Mg_2/3Nb_4/3O₇ (BMN) pyrochlore films deposited on Cu/Si substrates at low temperatures are characterized for structural and dielectric properties as a function of oxygen flow rate. BMN films deposited at 150 °C were partially crystallized with nano-sized crystallines of approximately 8.7 nm. The dielectric properties of films are independent on variation of an oxygen flow rate, but the lowest leakage current densities observed in the range between 10 and 30 sccm(standard cc/min). BMN films (50 nm-thick) deposited at 100 °C and an oxygen flow rate of 30 sccm show a capacitance density of 570 nF/cm² and a breakdown voltage of 3 V.     

Optimization design on breakdown voltage of AlGaN/GaN high-electron mobility transistor

Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2×10¹⁶ to 5×10¹⁹ cm^-3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons'' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices.     

4H–SiC BJTs with current gain of 110

4H–SiC BJTs with a common emitter current gain of 110 have been demonstrated. The high current gain was attributed to a thin base of 0.25 μm which reduces the carrier recombination in the base region. The device open base breakdown voltage (BV_CEO) of 270 V was much less than the open emitter breakdown voltage (BV_CBO) of 1560 V due to the emitter leakage current multiplication from the high current gain by “transistor action” of BJTs. The device has shown minimal gain degradation after electrical stress at high current density of >200 A/cm²up to 25 h.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.