A comprehensive model for PMOS NBTI degradation: Recent progress

Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.     

A thorough investigation of MOSFETs NBTI degradation

An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, the influence of different process splits as the gate oxide nitridation, the nitrogen content, the source/drain implant and poly doping level on the NBTI degradation is investigated and discussed with our present understanding.     

A comprehensive model for oxide degradation

In this work we present two analytical (and physically supported) models to describe trap kinetics in both thin and ultra-thin SiO₂ films. The models are based on the different mechanism controlling the carrier transport through the oxides and on the assumption of a two step process for creating stable traps, through defect precursors. Experimental data of stress induced leakage current confirm the validity of models predictions. Furthermore, a systematic study of the transient of trap kinetics experimentally demonstrates the existence of defect precursors as well as a reduction of oxide damage under pulsed stress condition respect to DC case.     

28 nm PMOS器件中Ge注入对NBTI可靠性的影响

研究了28 nm 多晶硅栅工艺中Ge注入对PMOS器件的负偏压温度不稳定性(NBTI)的影响。在N阱中注入Ge,制作了具有SiGe沟道的PMOS量子阱器件。针对不同栅氧厚度和不同应力条件的器件,采用动态测量方法测量了NBTI的退化情况,采用电荷泵方法测量了界面态的变化情况。实验结果表明,由于Ge的注入,PMOS器件中饱和漏电流的退化量降低了43%,同时应力过程中产生的界面态得到减少,有效提高了PMOS器件的NBTI可靠性。     

NBTI degradation in STI-based LDMOSFETs

NBTI degradation in STI-based LDMOSFETs has been investigated by multi-region DCIV spectroscopy (MR-DCIV), a non-destructive and sensitive method to probe the interface states on channel, accumulation and STI region. A unified MR-DCIV current model was proposed based on its independency to the forward bias and temperature. Under the same negative gate stress condition, MR-DCIV current degradation was compared for nLDMOSFET and pLDMOSFET. Much larger MR-DCIV current shift was observed at channel and accumulation region with thin gate oxide thickness, indicating interface states generation at related regions. Our results show that more significant degradation for multi-finger device was consistent with NBTI degradation mechanism. High voltage device design with thermal management consideration is of crucial importance to guaranteeing the device performance and reliability.     

Transistor network restructuring against NBTI degradation

Negative Bias Temperature Instability (NBTI) has become a critical reliability concern for nanometer PMOS transistors. A logic function can be designed by alternative transistor networks. This work evaluates the impact of the NBTI effect in the delay of CMOS gates considering both the effect of intra-cell pull-up structures and the effect of decomposing the function into multiple stages. Intra-cell pull-up PMOS transistor arrangements have been restructured to minimize the number of devices under severe NBTI degradation. Also, circuits decomposed into more than one stage have been compared to their single stage design version. Electrical simulation results reveal that the restructuring of intra-cell transistor networks recovers up to 15% of rise delay degradation due to NBTI, while the decomposition of single stage circuit topologies into multi-stage topologies tends to reduce the rise degradation delay at a cost of fall delay degradation.     

A comprehensive modeling of dynamic negative-bias temperature instability in PMOS body-tied FinFETs

This paper presents a novel approach to estimate the rising and falling behavior of Nth-order ON-state current by dynamic negative-bias temperature instability (DNBTI), with a comparison between experimental data and a modified DNBTI model in PMOS body-tied FinFETs for the first time. The modified model was proposed to predict not only Nth-order DNBTI behavior but also temperature and stress bias effects. The fin-width dependence was analyzed, and different trends between silicon-on-insulator and body-tied FinFETs were explained with the extracted DNBTI model parameters: stress time, oxide-field strength, and temperature. The proposed model closely matched the measured static lifetime.     

NBTI degradation: From physical mechanisms to modelling

An overview of the evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, based on our new present understanding, a new characterization methodology is proposed, which would open the way to a more accurate determination of parameter shifts and thus allowing implementing the degradation into design rules.     

Study for pulse stress NBTI characteristics degradation stress

NBTI characteristic degradation of MOSFET is still one of important reliability physics in semiconductor device. Although it is well recognized that its degradation is recovered immediately after releasing DC test stress, it is also fact that the voltage which is applied to the gate electrode in most semiconductor device is an intermittent stress like pulse, not consecutive DC stress as NBTI test. Accurate NBTI lifetime prediction method under this pulse stress condition can afford an actual reliable lifetime. In this work, we considered the characteristic recovery phenomenon in pulse NBTI stress with MOSFET of TOSHIBA 40 nm and 90 nm CMOS process technology and examined a more realistic life prediction method.     

NBTI model development with regression analysis

In industry, negative bias temperature instability (NBTI) mechanism degradation models are derived from regression analysis of stress data. The model exponents vary for different technologies and manufacturers. We will show that limited sampling (using only one lot) and the misapplication of regression analysis are major contributors to the variation in model coefficients. Linearizing a nonlinear equation by taking logarithms will give more emphasis to smaller values and less to larger values.     

Lifetime prediction for PMOS and NMOS devices based on a degradation model for ate- ias- tress

The degradation behaviour of PMOS and NMOS devices after Gate-Bias-stress (GB-stress) was investigated. The observed saturation current decrease of p-channel devices after GB-stress is due to field-induced generation of interface states. The decrease of saturation current of n-channel devices after GB-stress can be interpreted by trapped electrons, which are tunneling from the substrate into the gate oxide. Based on the experimental lifetime results at stress conditions extrapolation models were formulated which allow the determination of lifetime after GB-stress both for n- and p-channel devices at real operation conditions.     

Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs

Negative Bias Temperature Instability (NBTI)-induced degradation for ultra-scaled and future-generation MOSFETs is investigated. Numerical simulations based on Reaction-Diffusion framework are implemented. Geometric dependence of degradation arising from the transistor structure and scaling is incorporated into the model. The simulations are applied to narrow-width planar triple-gate and surround-gate MOSFET geometries to estimate the NBTI reliability under several scaling scenarios. Unless the operating voltages are optimized for specific geometry of transistor cross section, the results imply worsened NBTI reliability for the future-generation devices based on the geometric interpretation of the NBTI degradation. A time-efficient and straightforward analysis is developed to predict the degradation. This compact model confirms the numerical simulations.     

Long-term NBTI degradation under real-use conditions in IBM microprocessors

Long-term measurement of bias temperature instability (BTI) degradation obtained from an on-chip sensor is presented. The sensor reports measurements periodically with a digital output. Implemented on IBM’s z196 enterprise systems using IBM 45 nm technology, it can be used to monitor long-term degradation under real-use conditions. Over 700 days worth of ring oscillator degradation data from customer systems is presented. The data obtained by this sensor are consistent with models based on accelerated testing.     

NBTI degradation and its impact for analog circuit reliability

A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors.     

A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits

We present an aging analysis which considers variations in chip environment and workload as they are caused by dynamic voltage or frequency scaling, power-down modes, etc. Therefore, we developed a model for NBTI degradation and recovery based on trapping/detrapping. Our model accurately describes the relaxation during detrapping, the quasi-permanent degradation and shows good agreement with measurements from a 65 nm technology. The aging analysis utilizes this model to consider variations in environment and workload. Results show that our analysis can be used for system-level design decisions and reduces substantially estimated degradation.     

Impact of NBTI on the temporal performance degradation of digital circuits

Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.     

NBTI and irradiation related degradation mechanisms in power VDMOS transistors

In this paper it is shown that NBT stress effects in previously irradiated devices are strongly dependent on the total dose received. Namely, in the case of low-dose irradiation the subsequent NBT stress seems to lead to further device degradation. On the other hand, in the case of devices previously irradiated to higher doses, NBT stress seems to have positive role as it practically anneals a part of radiation-induced degradation. The total dose received at which NBT stress almost completely anneals radiation-induced degradation is determined to be around 60 Gy.     

HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors

The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to its superior gate control capability and improved carrier transportation property. In this paper, hot carrier injection (HCI) and negative bias temperature instability (NBTI) behavior of n-type and p-type SNWTs with top-down approach is discussed. In addition to initial fast degradation and quick saturation of NBTI stress behavior, non-negligible impacts of electron traps on the stress/recovery characteristics in p-SNWTs with metal gate is found and characterized with a kind of combined I_g–I_d RTN technique. The NBTI behavior is modeled taking account of the impacts from unique structural nature of GAA SNWTs. NBTI induced performance degradation of the typical nanowire-based circuits is estimated based on the proposed model. In addition, stochastic degradation induced by single/few trap in the thin-body SNWTs is observed and analyzed.