A fluxless flip-chip bonding for VCSEL arrays using silver-coated indium solder bumps

Alloys of lead-tin system are the most common solder alloys used today. However, there are environmental and health issues concerning the toxicity of lead present in these lead-tin solder alloys. Also, the flux residue removal is mandatory and leads to environmental threats. More importantly, the use of flux may contaminate the optically active surface by organic residue leftover, and a conventional cleaning method may not be effective for optoelectronic assemblies. Therefore, it is necessary to look for fluxless soldering processes for soldering optoelectronic systems. In the present study, we have conducted low-temperature flip-chip bonding of vertical-cavity surface-emitting laser (VCSEL) arrays on a glass substrate that provides propagation paths of laser beams and also supports a polymeric waveguide. Considering both the die shear test and the spreading test, the appropriate bonding temperature and pressure using indium solder bump were found to be about 150/spl deg/C/500 gf. The fracture occured between the indium solder bump and the VCSEL chip pad during the die shear test. It is inferred that both the low bonding temperature and the oxide layer which is formed on the surface of the indium solder prevented the bump from interacting with the chip pad. We expect the thin silver layer coating on the indium bump to protect the inner indium solder from oxidation and to decrease the melting temperature of the indium solder. Thus, we try coating a thin silver layer onto the indium surface. An eutectic reaction occurs at 97 wt.% of In with an eutectic point of 144/spl deg/C and the outer silver layer interacts with indium to form a AgIn/sub 2/ compound layer due to the high interdiffusion coefficient. As a result, the thin silver layer coated on the solder bump is very effective to enhance the adhesion strength between the indium bump and the VCSEL chip pads by decreasing the melting temperature of the indium solder bump locally.     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

High-yield flip-chip bonding and packaging of low-threshold VCSEL arrays on sapphire substrates

Oxide-confined top-emitting 850 nm and bottom-emitting 980 nm vertical-cavity surface-emitting laser (VCSEL) 8/spl times/8 arrays were designed and fabricated for applications of optical interconnects. The arrays were flip-chip bonded onto sapphire substrates that contain complimentary metal-oxide-semiconductor (CMOS) driver and fan-out circuitries. The off-sited bonding contacts and minimized bonding force produced very high yield of the hybridization process without causing damage to the VCSEL mesas. The hybridized devices were further mounted either on printed circuit board (PCB) or in 68-pin pin-grid-array (PGA) packages. The transparent sapphire substrate allowed optical outputs from the top-emitting VCSEL arrays to transmit directly through without additional substrate removal procedure. Lasing thresholds below 250 /spl mu/A for 850 nm VCSELs and 800 /spl mu/A for 980 nm VCSEL were found at room temperature. The oxide confinement apertures of VCSELs were measured to be around 6 /spl mu/m in diameter. High-speed data transmission demonstrated a bandwidth of up to 1 Gbits/s per channel for these hybridized VCSEL transmitters.     

Flip-Chip Bonding of MEMS Scanner for Laser Display Using Electroplated AuSn Solder Bump

A MEMS scanner has been flip-chip bonded by using electroplated AuSn solder bumps. The microelectromechanical systems (MEMS) scanner is mainly composed of two structures having vertical comb fingers. To optimize the bonding condition, the MEMS scanner was flip-chip bonded with various bonding temperatures. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system was used to observe the microstructures of the joints and analyze the element compositions of them. The die shear strength increased as the bonding temperature increased. During the thermal aging test, the delamination occurred at the interconnection of the MEMS scanner bonded at 340 degC. It is inferred that the Au layer serving as pad metallization has been dissolved in the molten AuSn solder totally, and subsequently the Cr layer was directly exposed to the AuSn solder. Judging by the results of both die shear test and thermal aging test, the optimal bonding temperature was found to be approximately 320 degC. Finally, using this MEMS scanner, we obtained an optical scanning angle of 32deg when driven by the ac control voltage of the resonant frequency in the range of 22.1-24.5 kHz with the 100-V dc bias voltages     

Compact packaging of optical and electronic components for on-board optical interconnects

An optical interconnection plate was developed in order to achieve a compact and cost-effective interconnection module for an optical data link between chips on printed circuit boards. On the silica substrate, transmission lines and solder bumps are formed on the top surface of the substrate, and polymer waveguide array with 45/spl deg/ mirror planes is formed on the back side. This optical interconnection plate technique makes the alignment procedure quite simple and economical, because all the alignment steps between the optical components can be achieved in wafer processes and a high accuracy flip-chip bonding technique. We confirmed the sufficiently high coupling efficiency and low optical crosstalk using the simplified experimental setup. Flip-chip bonding of the vertical-cavity surface-emitting laser and photodiode arrays on the top surface of the optical interconnection plate was performed using indium bumps in order to avoid thermal damage of the polymer waveguide. The fully packaged optical interconnection plate showed an optical data link at rates of 455 Mb/s. Improvement of the mirror surface roughness and the mirror angle accuracy could lead to an optical link at higher rates. In addition, the interconnection system can be easily constructed by inserting the optical interconnection plate between the processing chips or data lines requiring optical links.     

RFID芯片超声倒装封装技术研究

超声倒装是近年来芯片封装领域中快速发展的一种倒装技术,具有连接强度高、接触电阻低、可靠性高、低温下短时完成和成本低的优势,特别适合较少凸点的RFID芯片封装。在镀Ni/Au铜基板上进行了RFID芯片超声倒装焊接实验,金凸点与镀Ni/Au铜基板之间实现了冶金结合,获得了良好的力学与电气性能,满足射频要求。     

凸点材料的选择对器件疲劳特性的影响

为了研究凸点材料对器件疲劳特性的影响,采用非线性有限元分析方法、统一型黏塑性本构方程和Coffin-Manson修正方程,对Sn3.0Ag0.5Cu,Sn63Pb37和Pb90Sn10三种凸点材料倒装焊器件的热疲劳特性进行了系统研究,对三种凸点的疲劳寿命进行了预测,并对Sn3.0Ag0.5Cu和Pb90Sn10两种凸点材料倒装焊器件进行了温度循环试验.结果表明,仿真结果与试验结果基本吻合.在热循环过程中,凸点阵列中距离器件中心最远的焊点,应力和应变变化最剧烈,需重点关注这些危险焊点的可靠性;含铅凸点的热疲劳特性较无铅凸点更好,更适合应用于高可靠的场合;而且随着铅含量的增加,凸点的热疲劳特性越好,疲劳寿命越长.     

The application of flip-chip bonding interconnection technique on the module assembly of 10 Gbps laser diode

Flip chip bonding technique using Pb/In solder bumps was applied to packaging of a 10 Gbps laser diode (LD) submodule for high speed optical communication systems. The effect of the flip-chip bonding interconnection technique instead of conventional wire bonding was investigated for high speed broad band devices. The broad band performance of 10 Gbps LD submodule was simulated using SPICE S/W and compared with experimental results. In this simulation, the 10 Gbps LD was modeled in a parallel RC circuit. The values of R and C used for the equivalent circuit were 5ω and 1 pF, respectively. The LD was placed in series with a 18ω thin film resistor to prevent the impedance mismatch between the LD and a 25ω transmission line. The dependence of parasitic parameters on the small signal modulation bandwidth and the scattering parameters of the LD submodule was investigated and analyzed up to 20 GHz. A small signal modulation bandwidth of 14 GHz at 10 mA dc bias current and the clean modulation response up to 20 GHz were found for the flip-chip bonded submodule. The bandwidth of flip-chip bonded 10 Gbps LD submodule is wider than that of the wire-bonded LD submodule by a difference of 3.8 GHz.     

Gold Stud Bumps Flip-Chip Bonded onto Copper Electrodes with Titanium and Silver Layers

The purpose of this study was to develop the thermosonic flip-chip bonding process for gold stud bumps bonded onto copper electrodes on an alumina substrate. Copper electrodes were deposited with silver as the bonding layer and with titanium as the diffusion barrier layer. Deposition of these layers on copper electrodes improves the bonding quality between the gold stud bumps and copper electrodes. With appropriate bonding parameters, 100% bondability was achieved. Bonding strength between the gold stud bumps and copper electrodes was much higher than the value converted from the standards of the Joint Electron Device Engineering Council (JEDEC). The effects of process parameters, including bonding force, ultrasonic power, and bonding time, on bonding strength were also investigated. Experimental results indicate that bonding strength increased as bonding force and ultrasonic power increased and did not deteriorate after prolonged storage at elevated temperatures. Thus, the reliability of the high-temperature storage (HTS) test for gold stud bumps flip-chip bonded onto a silver bonding layer and titanium diffusion barrier layer is not a concern. Deposition of these two layers on copper electrodes is an effective and direct method for thermosonic flip-chip bonding of gold stud bumps to a substrate, and ensures excellent bond quality. Applications such as flip-chip bonding of chips with low pin counts or light-emitting diode (LED) packaging are appropriate.     

Ultralow-threshold sapphire substrate-bonded top-emitting 850-nm VCSEL array

Oxide-confined top-emitting vertical-cavity surface-emitting-laser (VCSEL) 8 /spl times/ 8 arrays were designed and fabricated with ultralow thresholds. The arrays were flip-chip bonded onto sapphire substrates and mounted in pin-grid-array packages as optical transmitter arrays. By using the offset-contact bonding process, we were able to obtain very high yield for hybridized devices without damaging the VCSEL mesas. Room-temperature lasing thresholds below 70 /spl mu/A were found from some of these packaged VCSELs with measured oxide apertures 2.6 /spl mu/m in diameter. The emission spectrum at an injection current of 70 /spl mu/A showed a full-width at half-maximum linewidth of less than 2.5 A. Polarization properties were also confirmed from the output of the device. The superior performance was attributed to the optimized size and placement of the confinement aperture and the precise alignment of the gain profile of the active region to the mode of the resonant cavity.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

Hybrid integration of surface-emitting microlaser chip and planaroptics substrate for interconnection applications

The bonding of a monolithic array of surface-emitting microlasers onto a glass substrate that contains a matching array of microlenses and mirrors is reported. The bonding was achieved by flip-chip solder bump bonding using indium as the solder material. The alignment precision is within ±2 μm. The optical substrate provides a simple interconnection scheme that routes the light from each laser to well defined output positions     

Vertical InGaN light-emitting diodes with Ag paste as bonding layer

Vertical InGaN-based light-emitting diodes (LEDs) were fabricated with a Si substrate using Ag paste as bonding layer. Vertical LEDs with Ag paste bonding layer were bonded with Si substrate at a low temperature of 140 °C. In addition to the low-temperature bonding process, the soft property of Ag paste could better alleviate thermal stress compared with conventional eutectic metal bonding layer such as Au–Sn. Under the same test conditions, these two LEDs showed similar optical and electrical properties and reliability. However, LEDs with Ag-paste bonding layer were fabricated through a low-temperature bonding process. The characteristic of soft solder enables a relatively wider process window, such as bonding pressure and temperature, and a higher yield as compared with the vertical LEDs with Au–Sn eutectic bonding layer.     

混成式焦平面阵列芯片倒装互连技术研究

介绍了为保证倒装焊接性能,设备所采取的措施。对比了不同形貌铟柱的优缺点,分析了互连可靠性与铟柱高度的关系,介绍了考核互连可靠性的方法。通过互连技术研究,我们实现了较高性能的倒装互连,互连条件选择温度在60℃-140℃范围,压力范围0．1克／铟柱-0．5克／铟柱。互连连通率〉99．9％,互连后的芯片组件在低温（77K）与常温（23℃）间不少于100次的反复冲击的情况下,测试接触性能及InSb二极管性能都无变化,满足了互连器件可靠性要求。     

Indium bump array fabrication on small CMOS circuit for flip-chip bonding

We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64×64 indium arrays with 20μm-high,30μm-diameter bumps are successfully formed on a 5×6.5 mm~2 CMOS chip.     

Electroplated indium bump arrays and the bonding reliability

A novel electroplating indium bumping process is described,as a result of which indium bump arrays with a pitch of 100μm and a diameter of 40μm were successfully prepared.UBM(under bump metallization) for indium bumping was investigated with an XRD technique.The experimental results indicate that Ti/Pt(300(?)/200(?)) has an excellent barrier effect both at room temperature and at 200℃.The bonding reliability of the indium bumps was evaluated by a shear test.Results show that the shear strength of the ind...     

Three-dimensional waveguide arrays for coupling between fiber-optic connectors and surface-mounted optoelectronic devices

This paper describes the fabrication of novel surface-mountable waveguide connectors and presents test results for them. To ensure more highly integrated and low-cost fabrication, we propose new three-dimensional (3-D) waveguide arrays that feature two-dimensionally integrated optical inputs/outputs and optical path redirection. A wafer-level stack and lamination process was used to fabricate the waveguide arrays. Vertical-cavity surface-emitting lasers (VCSELs) and photodiodes were directly mounted on the arrays and combined with mechanical transferable ferrule using active alignment. With the help of a flip-chip bonder, the waveguide connectors were mounted on a printed circuit board by solder bumps. Using mechanical transferable connectors, which can easily plug into the waveguide connectors, we obtained multi-gigabits-per-second transmission performance.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

Preparation of Sn-Ag-In ternary solder bumps by electroplating in sequence and reliability

This paper describes a technique that can obtain ternary Sn-Ag-In solder bumps with fine pitch and homogenous composition distribution.The main feature of this process is that tin-silver and indium are electroplated on copper under bump metallization（UBM） in sequence.After an accurate reflow process,Sn_1.8Ag_9.4In solder bumps are obtained.It is found that the intermetallic compounds（IMCs） between Sn-Ag-In solder and Cu grow with the reflow time,which results in an increase in Ag concentration in the solder area.So during solidification, more Ag₂In nucleates and strengthens the solder.     

分步电镀法制备Sn-Ag-In三元凸点及其可靠性

本文介绍了一种制备细节距、元素分布均匀的Sn-Ag-In三元凸点的方法。其特征在于在Cu凸点下金属层上分步电镀Sn-Ag和In,通过精确控制回流过程,获得了Sn1.8Ag9.4In凸点。研究发现位于Sn-Ag-In焊料和Cu之间的金属间化合物厚度随回流时间的延长而生长,这使得焊料基体中Ag相对浓度增加,因此在凝固过程中,更多的Ag2In相析出,起到了颗粒增强的作用。