芯片级尺寸封装返修技术工艺评定

与传统表面安装器件（SMD）方形扁平封装（QFP）相比,芯片规模封装（CSP）及焊球阵列封装（BGA）在元件尺寸方面显著缩减。回流后在芯片下方形成焊点的位置表明,目检是不可能的。对有缺陷的芯片而言,返修的唯一方法就是除去并替换该芯片。虽然元件拆除易于完成,但替换过程也许更复杂。比较两种PCB焊盘清洗方法并从最后的焊盘抛光得出结论,在第一个工艺技术中,采用热氮气脱焊技术回流焊盘上的任何残余焊料,并通过液化真空除去。第二个技术工艺涉及到使用网状焊料芯吸法及有刀片尖的焊接烙铁来除去PCB焊盘上的残余焊料。评定的四个淀积技术工艺,包括最小型模板、浸渍传递、接触及非接触模压技术。最小型模板用于把焊膏淀积到返修的元件部位的电子制造业的传统方法。     

影响BGA封装焊接技术的因素研究

虽然表面贴装制造工艺已经纯熟,但是随着BGA封装的广泛应用以及焊球间距的逐步减小,给表面贴装制造工艺带来了新的挑战.基于BGA封装在表面贴装技术焊接中的应用,从印制电路板焊盘设计、印制电路板板材选取和保护、BGA封装选取和保护、印刷工艺、回焊炉温度曲线设定与控制等方面,阐述了影响BGA封装焊接技术的各个因素,进而提升B...     

Ethylene glycol ether free solder paste development

There are growing concerns in the electronics industry for not only finding alternatives to lead but also other potentially hazardous materials as well. This paper summarizes the development of ethylene glycol ether (EGE)-free solder flux for the formulation of lead-free solder pastes. Replacing the toxic components in the flux was only the first challenge, the criteria of commercially proven pastes also had to be met. Both commercial and in-house solder paste formulations were evaluated for printability, reflow, wetting, flux residue removal, and solder void characteristics. Two critical issues, solder bump boids and flux residue removal, were identified and associated with the high temperature reflow of Pb-free pastes. These issues were not effectively improved by the existing commercial EGE-free solder pastes. New solder paste formulations were developed utilizing alternative chemistry than those found in traditional solder paste fluxes. These pastes, some, of which are also water soluble, reduced void frequency and size by more than 4x as compared to vendors' pastes. Solder bump height uniformity of 135 4 m within each die was consistently achieved. Thermal-mechanical reliability tests were performed on various lead-free solder alloys using the new flux formulations. The reliability of flip chip assembled DCA on organic boards with both OSP/Cu and Cu/Ni/au pad metallizations were comparable to eutectic Sn63Pb37 bumped assemblies using commerical pastes.     

弯曲应力状况下微型BGA封装可靠性比较研究

微型球栅阵列（μBGA）是芯片规模封装（CSP）的一种形式,已发展成为最先进的表面贴装器件之一。在最新的IxBGA类型中使用低共晶锡．铅焊料球,而不是电镀镍金凸点。采用传统的表面贴装技术进行焊接,研讨μBGA的PCB装配及可靠性。弯曲循环试验（1000～1000με）,用不同的热因数（Qη）回流,研究μBGA、PBGA和CBGA封装的焊点疲劳失效问题。确定液相线上时间,测定温度,μBGA封装的疲劳寿命首先增大,接着随加热因数的增加而下降。当Q。接近500S·℃时,出现寿命最大值。最佳Qη范围在300-750s·℃之间,此范围如果装配是在氮气氛中回流,μBGA封装的寿命大于4500个循环。采用扫描电子显微镜（SEM）,来检查μBGA和PBGA封装在所有加热N数状况下焊点的失效。每个断裂接近并平行于PCB焊盘,在μBGA封装中裂纹总是出现在焊接点与PCB焊盘连接的尖角点,接着在Ni3Sn4金属间化合物（IMC）层和焊料之间延伸。CBGA封装可靠性试验中,失效为剥离现象,发生于陶瓷基体和金属化焊盘之间的界面处。     

Solder thickness variation with respect to soldering parameters

This study investigated the growth behavior of solder interconnect on solder bonding pad. The solder thickness was investigated with respect to parameters including bonding pad area, reflow temperature, solder paste volume, loading, and die size (metallization area). Solder thickness was found to have a maximum value with respect to the ratio of solder paste volume to pad size. Loading and the reflow temperature showed no effect on solder thickness. An enlargement in metallization area reduces the solder thickness, while greater solder paste volume increases the solder thickness     

Double bump flip-chip assembly

Capillary underfill remains the dominate process for underfilling Hip-chip die both in packages and for direct chip attach (DCA) on printed circuit board (PCB) assemblies. Capillary underfill requires a post reflow dispense and cure operation, and the underflow time increases with increasing die area and decreasing die-to-substrate spacing. Fluxing or no-How underfills are dispensed prior to die placement and cure during the solder reflow cycle. Since filler particles in the fluxing underfill can be trapped between the solder ball and the substrate pad during placement, the filler content of fluxing underfills is typically limited to <20% or assembly yield drops dramatically. At 20% filler concentration, the coefficient of thermal expansion (CTE) of the underfill is near that of the bulk resin (50-80 ppm//spl deg/C). In this paper, a double bump Hip-chip process is described. A filled capillary underfill is coated onto a wafer and cured. The wafer is then polished to expose the solder bumps. A second solder bump is formed over the original bump by stencil printing solder paste. After dicing, the die is assembled to the PCB using unfilled fluxing underfill. In the resulting structure, the low CTE underfill is near the low CTE Si die, and the higher CTE underfill is in contact with the PCB. In addition, the standoff height is increased compared to a conventional single bump assembly. In air-to-air thermal shock tests, the double bump assembly was /spl sim/ 1.5 X more reliable than the conventional single bump construction with fluxing underfill. Modeling results are also presented.     

Interfacial reaction study on a solder joint with Sn-4Ag-0.5Cu solder ball and Sn-7Zn-Al (30 ppm) solder paste in a lead-free wafer level chip scale package

The interfacial reactions of solder joints between the Sn-4Ag-0.5Cu solder ball and the Sn-7Zn-Al (30 ppm) presoldered paste were investigated in a wafer level chip scale package (WLCSP). After appropriate surface mount technology (SMT) reflow process on the printed circuit board (PCB) with organic solderability preservative (Cu/OSP) and Cu/Ni/Au surface finish, samples were subjected to 150°C high-temperature storage (HTS), 1,000 h aging. Sequentially, the cross-sectional analysis is scrutinized using a scanning electron microscope (SEM)/energy-dispersive spectrometer (EDS) and energy probe microanalysis (EPMA) to observe the metallurgical evolution in the interface and solder buck itself. It was found that Zn-enriched intermetallic compounds (IMCs) without Sn were formed and migrated from the presolder paste region into the solder after reflow and 150°C HTS test.     

Lead-free chip scale packages: assembly and drop test reliability

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.     

SnAgCu无铅焊膏用活性物质研究

以SnAgCu无铅焊膏铺展性能为主要指标,通过回流焊接实验,对用于助焊剂的17种有机酸活性物质进行了筛选。选取两种性能较好的有机酸配成复合活性物质,并对该活性物质的组成进行优化。用湿热试验测试焊后残留物的腐蚀性。结果表明:以羧基官能团比例为3:7的丁二酸和一元酸A混合物作为活性物质,并添加质量约0.66%的乙醇胺调整酸度,得到了pH值约为3的助焊剂;此助焊剂性能优良,可使焊点铺展率达到84%。使用含有此助焊剂的焊膏,采用回流焊接工艺在PCB板上贴装片式元件,所得焊点光亮饱满,且焊后残留物无腐蚀性,可以实现免清洗。     

Understanding the process window for printing lead-free solderpastes

Solder paste is primarily used as a bonding medium for surface mount assemblies (SMA) in the electronics industry, and is typically deposited using the stencil printing process. Stencil printing is a very important and critical stage in the reflow soldering of surface mount devices, and a high proportion of all SMA defects are related to this process. This is likely to continue with the drive toward the introduction of lead-free solder pastes. Work is continuing on the metallurgical properties of these lead-free solders, including solder joint strength and material compatibility. However, the initial challenge for the new Pb-free formulations is in achieving repeatable solder deposit from print to print and from pad to pad. To meet this challenge, new flux formulations are being developed. For a smooth transition to Pb-free soldering formulations, a proper understanding of the solder paste printing performance is necessary. The key parameters that affect solder paste printing have been identified and are the subject of numerous studies. In lead-free solder paste, the replacement of lead with other elements (including Bi, Cu) changes the density of this dense suspension. In this paper, we investigate the effects of printer parameters, i.e. squeegee speed and pressure (defined as the process window) on the printing performance of a variety of lead-free solder pastes. A three-level design of experiment on these factors was used. Comparisons are presented with lead-rich solder pastes. The metal content of the lead-free solders had a significant effect on the process window     

Plasma reflow bumping of Sn-3.5 Ag solder for flux-free flip chip package application

A new flux-free reflow process using Ar+10%H/sub 2/ plasma was investigated for application to solder bump flip chip packaging. The 100-/spl mu/m diameter Sn-3.5wt%Ag solder balls were bonded to 250-/spl mu/m pitch Cu/Ni under bump metallurgy (UBM) pattern by laser solder ball bonding method. Then, the Sn-Ag solder balls were reflowed in Ar+H/sub 2/ plasma. Without flux, the wetting between solder and UBM occurred in Ar+H/sub 2/ plasma. During plasma reflow, the solder bump reshaped and the crater on the top of bump disappeared. The bump shear strength increased as the Ni/sub 3/Sn/sub 4/ intermetallic compounds formed in the initial reflow stage but began to decrease as coarse (Cu,Ni)/sub 6/Sn/sub 5/ grew at the solder/UBM interface. As the plasma reflow time increased, the fracture mode changed from ductile fracture within the solder to brittle fracture at the solder/UBM interface. The off-centered bumps self-aligned to patterned UBM pad during plasma reflow. The micro-solder ball defects occurred at high power prolonged plasma reflow.     

A new bumping process using lead-free solder paste

In this paper, we report development of a new process for lead-free solder bumping with no flux residues, using stencil printing and hydrogen radicals, which can lessen both the environmental load and the manufacturing cost of solder bumping. In this process the reduction of the hydrogen radicals, instead of the flux, will eliminate the surface oxides of the stencil printed lead-free solder paste. Sn-3.0Ag-0.5Cu lead-free solder paste, which contains no residue flux was printed on an 8-in wafer. Hydrogen plasma was radiated for a minute during the reflow process, and the printed paste formed a bump. Reflow experiments without hydrogen radicals treatment were also carried out for comparison, where no successful reflow could be observed.     

Growth prediction of tin/copper intermetallics formed between 63/37 Sn/Pb and OSP coated copper solder pads for a flip chip application

This study quantifies the effect of temperature and time on the growth of Cu-Sn intermetallics, specifically for flip chip/ball grid array packaging technology. The activation energy and the growth rates were determined for solid state diffusion, after the initial assembly reflow(s). Three different types of solder joints were investigated. 1) BGA 63/37 solder joints which were formed by a standard convection oven attach of 30 mil (760 /spl mu/m)diameter solder spheres to OSP protected, Cu plated ball pads of an organic flip chip substrate. The ball pads are solder mask defined and of 0.635 mm nominal diameter. 2) Flip chip bump pad solder joint consisting of 63/37 eutectic solder bumped die attached to a nonsolder mask defined, OSP protected, Cu plated pad of the flip chip substrate. The flip chip bumps on the die are created by screen printing solder paste on the die pads and subsequent reflow attach, by a standard convection oven to the die under bump metallurgy (UBM). The nominal die UBM pad diameter is 0.085 mm. 3) Solder joint formed on a coupon which involved the reflow of the balls randomly placed on a Cu plated layer with no solder mask coating. The investigation was performed by first establishing the intermetallic growth rate at six different temperatures, ranging from 85/spl deg/C to 150/spl deg/C. The relationship between intermetallic growth and time was shown to essentially follow the common parabolic diffusion relationship to temperature especially above 100/spl deg/C. The activation energy (E/sub a/) and the growth constant (k/sub 0/) were then calculated from this data. The results showed that the E. for the total intermetallic thickness was essentially similar for the three solder joint configurations of the ball, bump and the coupon described above. E. varied from 0.31 eV to 0.32 eV, while the k/sub 0/ varied from 18.0 /spl mu/m/s/sup 1/2 / to 24.2 /spl mu/m/s/sup 1/2 /.     

An overview of solder bump shape prediction algorithms withvalidations

The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range     

无铅焊料十温区回流焊过程的仿真研究

通过对回流焊接工艺参数传输带速度、各个炉区温度设定和焊膏熔化温度曲线的关系研究,建立了大尺寸PCB组件传热过程的数学模型。基于ANSYS平台,模拟了无铅焊料PCB组件在十温区回流焊接过程中的温度场,从而确定了合适的焊接参数。     

Reliable Lead-Free Rework Process for Stacked CSP Components

Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The complex nature of stacked chip-scale package (CSP) components coupled with a lead-free process presents unique rework challenges that needed to be studied and addressed. Reworking a CSP is complicated as the solder joints are hidden underneath the component. The process window available for the lead-free rework process is very narrow. There are number of other critical factors, which complicate and affect the repeatability of the rework process. The complications only increase with the use of stacked CSP devices. The rework of package stacked CSP components, which are complex in nature, is a daunting task. The key issues and observations with regard to the issues and challenges associated with the lead-free rework of mirror-imaged package stacked CSP components has been presented in this paper. In addition, the paper also provides a recipe for reliably reworking these packages.     

Solder balling of lead-free solder pastes

Solder balling in Sn/Ag/Cu solder pastes was studied in this work. Three different solder pastes, several different reflow profiles and conditions, and two stencil thicknesses were used in the investigation. During the first phase, called the verification phase, the solder pastes were checked to ensure they met the minimum requirements. In the process-screening phase, the reflow profile was varied. Results show that besides flux chemistry, reflow atmosphere plays the major role in solder balling. The average number of solder balls with the best paste was one fifth of that with the worst paste. Furthermore, with all the pastes, the number of solder balls dropped close to zero when nitrogen atmosphere was used. Another finding during the reflow process screening was the influence of the stencil thickness on the solder-balling result. With a thinner stencil, two of the pastes exhibited significant solder balling. This is assumed to be caused by the different ability of fluxes to withstand oxidation during the preheating in the reflow process. In the last phase, the effect of the solder-paste particle size on solder balling was studied more closely. The flux chemistry was kept unchanged, and the solder particle size was varied between type 3 and type 4. The results show that, with type 4 paste, significantly more solder balls are formed compared to type 3 paste. It was also confirmed that, regarding the reflow profile, the ramp-up rate from 150°C to 217°C and the reflow atmosphere were the most significant factors that determine the solder-ball formation for both types of paste.     

无铅喷锡(HASL)润湿不良问题及对策

针对东莞康佳电子有限公司生产无铅喷锡(HASL)PCB板时所遇到的焊盘润湿不良问题,采用了正常PCB板材与异常PCB板材对比,对smt生产制程条件进行内检等方法措施,以及最终对焊盘异常的PCB送国家级实验室5所分析结论确认焊盘润湿不良问题的主要表现为锡膏对PCB焊盘润湿不良,造成不良的主要原因与PCB焊盘HASL表面不平整以及焊盘已发生合金化降低其可焊性有关。并在批量生产中采取烘烤箱使用105±5℃,烘烤4小时烘烤PCB和使用酒精擦洗PCB焊盘来减少润湿不良的方法措施保证生产。     

Sn–Ag–Cu Soldering Reliability as Influenced by Process Atmosphere

To develop an optimal surface mount reflow soldering process with Sn–Ag–Cu, the influences of atmosphere and cooling speed on soldering reliability have been examined by using Sn plated chip components and of Pd plated small outline packages (SOPs) on a printed circuit board (PCB). Typical three Sn–Ag–Cu alloy pastes, i.e., Sn–3.0wt%Ag–0.5wt%Cu, Sn–3.8wt%Ag–0.75wt%Cu, and Sn–4.0wt%Ag–0.9wt%Cu, were used for reflow soldering in air or ${hbox {N}} _{2}$ atmospheres. In the case of chip component joints, the solder compositions, cooling speed, and atmospheres during reflow treatment slightly affect the dendritic microstructure of the solder fillets. In contrast, these parameters rarely affect the solder wettability both on boards/components and shear strengths of the solder joints. In the case of the SOP joints, however, the atmospheres in reflow treatment and the fluxes strongly affect the appearances of solder fillet surfaces structure. Despite the types of solder fluxes, ${hbox {N}} _{2}$ process atmosphere obviously improved wettability of the solders on the lead-frames of the SOP. Moreover, the scatter in shear strengths becomes smaller and the wetting of solders on the lead-frames becomes stabler in ${hbox {N}} _{2}$ atmosphere than in air atmosphere.      

低银无铅焊膏板级封装工艺和焊点可靠性试验

针对低Ag无铅焊膏的市场需求,研究开发了一种适用于99.0Sn0.3Ag0.7Cu低Ag无铅焊膏用松香型无卤素助焊剂(WTO—LF3000),配制了相应的无铅焊膏(WTO—LF3000—SAC0307),并对其板级封装工艺适应性及焊点可靠性进行了考察,用测试后样品的电气可靠性作为接头可靠性评价条件。结果表明:所开发的低Ag无铅焊膏熔点和润湿性符合产品实际要求。配制的焊膏印刷质量良好,焊点切片观察其孔隙率<25%,满足行业标准IPC—A—610D之要求。样品分别经跌落、震动和温度循环试验后,无焊点脱落等现象,电气功能正常。