Studies of photoconductance decay method for characterization of near-surface electrical properties of semiconductors

The Photoconductance Decay (PCD) method in a standard version allows determination of the bulk properties of semiconductors but is not suitable for evaluation of the surface and near-surface region of the wafer during processing. This experiment is concerned with PCD measurements devised specifically for the purpose of electrical probing using temporary contacts of the near-surface (ns-PCD) region of semiconductor substrates, including thin films. The method is tested through the measurements of the single-crystal, indirect bandgap elemental semiconductor wafers (Si and Ge), as well as selected direct bandgap compound semiconductor wafers (GaAs and InP). In the former case, surface properties of the material tested are altered in a controlled fashion and the PCD response to the surface alteration, in terms of the minority carrier lifetime, is measured. In the case of all substrates studied, a direct correlation between carrier lifetime measured using PCD and the condition of the wafer surface was observed. Furthermore, the ns-PCD method was proven very effective in measuring minority carrier lifetime at the semiconductor-dielectric interface without having to form MOS test structures. The results obtained suggest that the modified PCD method employing temporary contacts to the measured surface can be used to monitor the condition of semiconductor surfaces during device processing.     

几种单晶半导体材料在压痕下的变形与断裂行为比较

采用显微压痕方法研究了Si、Ge、GaAs和InP四种半导体单晶的变形与断裂行为.通过测量[100]取向单晶体面内的显微硬度,裂纹开裂的临界压痕尺寸以及断裂韧性,分析了这四种材料力学性能的面内各向异性行为.结果表明:在压痕载荷的作用下,Si和Ge的塑性变形以剪切断层为主,而GaAs和InP则通过滑移系的开动协调变形.[100]取向的Si、Ge、GaAs和InP四种单晶的面内显微硬度、弹性模量和断裂韧性表现出不同程度的各向异性.裂纹长度与压痕尺寸间的关系表明,与GaAs和InP相比,Si、Ge具有较小的临界压痕尺寸和拟合直线斜率,这一临界压痕尺寸和拟合直线斜率的变化规律分别与材料的硬度和断裂韧性的变化规律一致.     

Polishing of semiconductor materials

Different abrasive processes such as grinding and lapping are necessary to produce semiconductor wafers. However grinding and lapping leads to deterioration of the surface integrity of monocrystalline wafers. Therefore polishing and planarization is of utmost importance to produce microelectronic components. In this lecture the basics of polishing technology as well as different process models are presented. Additionally the properties of different semiconductor substrate materials Si, GaAs are discussed.     

Catalyst-referred etching of silicon

A Si wafer and polysilicon deposited on a Si wafer were planarized using catalyst-referred etching (CARE). Two apparatuses were produced for local etching and for planarization. The local etching apparatus was used to planarize polysilicon and the planarization apparatus was used to planarize Si wafers. Platinum and hydrofluoric acid were used as the catalytic plate and the source of reactive species, respectively. The processed surfaces were observed by optical interferometry, atomic force microscopy (AFM) and scanning electron microscopy (SEM). The results indicate that the CARE-processed surface is flat and undamaged.     

Reflectance reduction of InP wafers after high-temperature annealing

Broadband reduction of light reflection from the surface of InP wafers after high-temperature annealing in air has been observed. In the transparency region of the material, the reflection drop is accompanied by increasing transmission of light through the wafer. The spectral position of a deep minimum of the reflection coefficient can be tuned, by varying the temperature and the time of annealing, in a wide spectral range from ultraviolet to infrared. The effect is due to formation of thermal oxide layers on the surfaces of the wafer with optical parameters favorable for antireflection.     

CRACK FACE INTERACTIONS AND NEAR-THRESHOLD FATIGUE CRACK GROWTH

Rough fracture surfaces usually influence substantially the fatigue growth properties of materials in the regime of low growth rates. Friction, abrasion, interlocking of fracture surface asperites and fretting debris reduce the applied load amplitude to a smaller effective value at the crack tip (“sliding crack closure”, or “crack surface interaction” or “crack surface interference”). The influence of these phenomena on the fatigue crack growth properties of structural steel is discussed and compared for the two kinds of mixed mode loading employed in this work. Mixed mode loading was performed by (A): cyclic mode III + superimposed static mode I and (B): cyclic mode I + superimposed static mode III loading. Such loading cases frequently occur in rotating load-transmission devices. Several differences are typical for these two mixed-mode loading cases. A superimposed static mode I load increases the crack propagation rate under cyclic mode III loading whereas cyclic mode I fatigue crack propagation is retarded when a static mode III load is superimposed. Increase of the R -ratio (of the cyclic mode III load) leads to an insignificant increase of fracture surface interaction and subsequently to a small decrease of the crack growth rate for cyclic mode III loading, whereas higher R -values during cyclic mode I+ superimposed static mode III loading lead to a significant reduction of the crack growth rates.     

Mechanical Strength of Silicon Wafers Cut by Loose Abrasive Slurry and Fixed Abrasive Diamond Wire Sawing

This paper reports on the mechanical strength of polycrystalline silicon wafers cut by loose abrasive slurry and fixed abrasive diamond wire sawing processes. Four line bending and biaxial flexure tests are used to evaluate the fracture strength of the wafers. Fracture strength of the wafers depends on the location, size, and orientation of microcracks in the silicon wafer and the distribution and magnitude of applied stresses. Measurement of microcracks at the wafer edge and center shows that edge cracks are typically larger than center cracks. Fixed abrasive diamond wire sawn wafers are found to have a higher crack density but smaller average crack length. Wafer fracture in four line bending is found to be primarily due to the propagation of edge cracks while center cracks are found to be the primary cause of wafer failure in biaxial flexure tests. Fracture mechanics based analyses demonstrate that crack orientation plays a significant role in four line bending, but not in biaxial flexure. Correlations of the wafer fracture strength and critical crack length agree well with microcrack measurements. The fracture strength of diamond cut wafers is found to be comparable or superior to the strength of slurry cut wafers.     

Ultra-high vacuum direct bonding of a p-n junction GaAs wafer using low-energy hydrogen ion beam surface cleaning

Low-energy hydrogen ion bombardment is used to clean GaAs surfaces. The hydrogen ions produce contamination-free surfaces without changes in surface composition (stoichiometry) and surface roughness. The wafers were brought into contact at room temperature after cleaning under ultra-high vacuum (UHV), and bonded over the whole area (2 inches) without application of external mechanical pressure. After bonding, the p-GaAs/n-GaAs wafer pair was annealed at 200 °C for 30 min under UHV conditions (<5×10⁻¹⁰ mbar) to improve the interface bonding strength and to achieve a full-area wafer bonding.Infrared (IR) imaging of the as-bonded wafers directly reveal the real bonding behaviour. High-resolution transmission electron microscopy images reveal that the wafers have been directly bonded without damage of the crystal lattice or intermediate layer and the interface is smooth. Current-voltage characterization shows near-ideal forward characteristics and the recombination in p-n junction space charge region.     

On the scribing and subsequent fracturing of silicon semiconductor wafers

The integrated circuits deposited on silicon wafers are often separated by scribing with a diamond tool followed by bending to produce fracture. Using a commercial scribing tool we find permanent deformation and three types of crack. The median crack which propagates downwards is the objective of the scribing process. Lateral cracks which form, apparently following plastic deformation, may lead to chipping on either side of the scribing tool. These cracks and also the chevron cracks which form on the surface are very similar to cracks observed in scratching glass. However, in silicon, because of its anisotropy, the chevron cracks may be a serious problem since they can guide the median crack out of the scribing direction onto a preferred cleavage plane. This aspect leads to a brief discussion of the crystallography of silicon and recommendations for scribing configurations which should minimize undesired fracture. Finally, it is shown that the established methods of linear elastic fracture mechanics may be used to predict the maximum radius of curvature required to fracture a wafer containing a prescribed series of median cracks.     

Evaluation of InP-to-silicon heterobonding

In this paper, we evaluate hydrophilic (HP) and hydrophobic (HB) surface pre-treatments in InP-to-Si direct wafer bonding. Surface roughness and surface chemistry was examined using atomic force microscopy and X-ray photoelectron spectroscopy, respectively. After bonding, the bonded interfaces were evaluated using infrared transmission imaging, bond-strength and current–voltage (I–V) measurements. It was found that HP surface treatment using oxygen plasma makes room temperature bonding of InP and Si very spontaneous, and results in high bond-strengths already after low-temperature annealing. This was not observed when using standard oxidising acids as HP surface treatment before bonding. HB InP and Si surfaces, also, did not prove to bond spontaneously at room temperature and the bond-strength started to increase only after annealing at about 400°C. HB bonding and annealing at 400°C was though the best choice regarding the electrical characteristics of the bonded InP/Si heterojunction.     

Strength and sharp contact fracture of silicon

The fracture strength of Si is considered in the context of yield and reliability of microelectronic and microelectromechanical (MEMS) devices. An overview of Si fracture, including the strength of Si wafers, dice and MEMS elements, highlights the importance of understanding sharp contact flaws, with their attendant residual stress fields, lateral cracks and strength-limiting half-penny cracks in advanced Si device manufacturing. Techniques using controlled indentation flaws, including measurements of hardness, crack lengths, crack propagation under applied stress, and inert and reactive strengths, are applied in an extensive new experimental study of intrinsic, n- and p-type {100} and {110} Si single crystals and polycrystalline Si, addressing many of the issues discussed in the overview. The new results are directly applicable in interpreting the strengths of ground or diced Si wafer surfaces and provide a foundation for studying the strengths of MEMS elements, for which the strength-controlling flaws are less well-defined. Although the indentation fracture behavior of Si is shown to be quite anisotropic, the extensive lateral cracking greatly affects crack lengths and strengths, obscuring the underlying single crystal fracture anisotropy. No effects of doping on fracture are observed. Strength decreases in water and air suggest that Si is susceptible to reactive attack by moisture, although the effect is mild and extremely rapid. Strength increases of indented components after buffered HF etching are shown to be due to reactive attack of the contact impression, leading to residual stress relief.     

Formation of subsurface cracks in silicon wafers by grinding

Single-crystal silicon is an important material in the semiconductor and optical industries.However,being hard and brittle,a silicon wafer is vulnerable to subsurface cracks(SSCs)during grinding,which is detrimental to the performance and lifetime of a wafer product.Therefore,studying the formation of SSCs is important for optimizing SSC-removal processes and thus improving surface integrity.In this study,a statistical method is used to study the formation of SSCs induced during grinding of silicon wafers.The statistical results show that grinding-induced SSCs are not stochastic but anisotropic in their distributions.Generally,when grinding with coarse abrasive grains,SSCs form along the cleavage planes,primarily the{111}planes.However,when grinding with finer abrasive grains,SSCs tend to form along planes with a fracture-surface energy higher than that of the cleavage planes.These findings provide a guidance for the accurate detection of SSCs in ground silicon wafers.     

Modelling of Surface Crack Growth under Lubricated Rolling–Sliding Contact Loading

The paper describes modelling approach to computational simulation of surface crack growth subjected to lubricated rolling–sliding contact conditions. The model considers the size and orientation of the initial crack, normal and tangential loading due to rolling–sliding contact and the influence of fluid trapped inside the crack by a hydraulic pressure mechanism. The motion of the contact sliding load is simulated with different load cases. The strain energy density (SED) and maximum tangential stress (MTS) crack propagation criteria are modified to account for the influence of internal pressure along the crack surfaces due to trapped fluid. The developed model is used to simulate surface crack growth on a gear tooth flank, which has been also experimentally tested. It is shown that the crack growth path, determined with modified crack propagation criteria, is more accurately predicted than by using the criteria in its classical form.     

Scanning Probing of the Tribovoltaic Effect at the Sliding Interface of Two Semiconductors

Contact electrification (CE or triboelectrification) is a common phenomenon, which can occur for almost all types of materials. In previous studies, the CE between insulators and metals has been widely discussed, while CE involving semiconductors is only recently. Here, a tribo-current is generated by sliding an N-type diamond coated tip on a P-type or N-type Si wafers. The density of surface states of the Si wafer is changed by introducing different densities of doping. It is found that the tribo-current between two sliding semiconductors increases with increasing density of surface states of the semiconductor and the sliding load. The results suggest that the tribo-current is induced by the tribovoltaic effect, in which the electron–hole pairs at the sliding interface are excited by the energy release during friction, which may be due to the transition of electrons between the surface states during contact, or bond formation across the sliding interface. The electron–hole pairs at the sliding interface are subsequently separated by the built-in electric field at the PN or NN heterojunctions, which results in a tribo-current, in analogy to that which occurs in the photovoltaic effect.     

A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.     

Performance of GaN vertical light emitting diodes using wafer bonding process with Al-alloyed graphite substrate

We report on the vertical-structure light emitting diodes (VLEDs) fabricated with wafer bonding method using Al-alloyed graphite and Si supporter. VLEDs with Al-alloyed graphite produced no crack during/after laser lift-off (LLO) techniques while the wafer crack took place using Si supporter because of the difference of thermal expansion coefficients between Si and sapphire. The performance of VLEDs with wafer bonding method using Al-alloyed graphite supporter was compared to those fabricated by Cu plating methods. The output power of the chips with wafer bonding method was nearly same as the one with Cu-plating method. However, the forward voltage of VLEDs with wafer bonding method was higher than those with Cu-plating method. In the terms of reliabilities the wafer bonding process is more preferable to Cu-plating and our report proposes that Al-alloyed graphite could be one of promising candidates for the supporters in wafer bonding process.     

Precise chemical analysis development for Si and GaAs surfaces

Precise chemical analysis (PCA) was developed to allow the study of non-interconnected atoms on crystalline semiconductor surfaces, such as those produced during rapid thermal processing (RTP) of silicon and electron beam lithography on gallium arsenide (GaAs). The PCA method is based on selectively dissolving the different components present on the semiconductor surface using preferential etchant solutions. After etching, the etchant solution, containing the etched component, is analyzed by a photometric technique. In this paper, we present photometric measurements of the amount of free (non-interconnected) atoms that remain on semiconductor surfaces following electron beam and RTP processing. In this context, free atoms are those presenting in any form other than crystalline GaAs or Si, for instance, those in the form of surface oxides. Using the PCA method, free Ga and As were detected on GaAs surfaces after electron beam lithography. Free silicon, boron and phosphorous atoms were found on silicon surfaces after RTP. The concentration of boron diffused into a silicon wafer during RTP was also carried out by means of slight surface etching. We estimate the accuracy of this PCA method at 2% for Ga and 5% for all other elements.     

A model-based clustering approach to the recognition of the spatial defect patterns produced during semiconductor fabrication

Defects on semiconductor wafers tend to cluster and the spatial defect patterns of these defect clusters contain valuable information about potential problems in the manufacturing processes. This study proposes a model-based clustering algorithm for automatic spatial defect recognition on semiconductor wafers. A mixture model is proposed to model the distributions of defects on wafer surfaces. The proposed algorithm can find the number of defect clusters and identify the pattern of each cluster automatically. It is capable of detecting defect clusters with linear patterns, curvilinear patterns and ellipsoidal patterns. Promising results have been obtained from simulation studies.     

Fracture behaviour of a TiAl alloy under various loading modes

Tensile tests, compression tests, in situ tensile tests, bending tests, tensile fatigue tests and bending fatigue tests were carried out for a TiAl alloy. Based on the global experimental results and microscopic observations of the fracture surfaces and cracking behaviour on the side surfaces of tested specimens, the fracture mechanisms of fully lamellar (FL) TiAl alloys under various loading modes are summarized as following: (1) Cracks initiate at grain boundaries and/or interfaces between lamellae. (2) When a crack extends to a critical length, which matches the fracture loading stress the crack propagates catastrophically through entire specimen. (3) The crack with the critical length can be produced promptly by the applied load in the tensile and bending test or be produced step-by-step by a much lower load in the fatigue tensile test. (4) For fatigue bending tests, the fatigue crack initiates and extends directly from the notch root, then extends step-by-step with increasing the fatigue bending loads. The fatigue crack maybe extends through entire specimen at a lower fatigue load or triggers the cleavage through the whole specimen at a higher load. (5) In compressive tests, cracks initiate and propagate in directions parallel or inclined to the compressive load after producing appreciable plastic strains. The specimen can be fractured by the propagation of cracks in both directions.     

Carbon molecular beam epitaxy on various semiconductor substrates

Direct graphene growth on semiconductor substrates is an important goal for successful integration of graphene with the existing semiconductor technology. We test the feasibility of this goal by using molecular beam epitaxy on various semiconductor substrates: group IV (Si, SiC), group III–V (GaAs, GaN, InP), and group II–VI (ZnSe, ZnO). Graphitic carbon has been formed on most substrates except Si. In general, the crystallinities of carbon layers are better on substrates of hexagonal symmetry than those on cubic substrates. The flatness of graphitic carbon grown by molecular beam epitaxy is noticeable, which may help the integration with semiconductor structures.