Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Polarity Effects of Polymer Gate Electrets on Non‐Volatile Organic Field‐Effect Transistor Memory

Organic non‐volatile memory (ONVM) based on pentacene field‐effect transistors (FETs) has been fabricated using various chargeable thin polymer gate dielectrics—termed electrets—onto silicon oxide insulating layers. The overall transfer curve of organic FETs is significantly shifted in both positive and negative directions and the shifts in threshold voltage (V_Th) can be systemically and reversibly controlled via relatively brief application of the appropriate external gate bias. The shifted transfer curve is stable for a relatively long time—more than 10⁵ s. However, this significant reversible shift in V_Th is evident only in OFETs with non‐polar and hydrophobic polymer electret layers. Moreover, the magnitude of the memory window in this device is inversely proportional to the hydrophilicity (determined from the water contact angle) and dielectric polarity (determined from the dielectric constant), respectively. Memory behaviors of ONVM originate from charge storage in polymer gate electret layers. Therefore, the small shifts in V_Th in ONVM with hydrophilic and polar polymers may be due to very rapid dissipation of transferred charges through the conductive channels which form from dipoles, residual moisture, or ions in the polymer electret layers. It is verified that the surface or bulk conductivities of polymer gate electret layers played a critical role in determining the non‐volatile memory properties.     

Tunable Crystal Nanostructures of Pentacene Thin Films on Gate Dielectrics Possessing Surface‐Order Control

To enhance the electrical performance of pentacene‐based field‐effect transistors (FETs) by tuning the surface‐induced ordering of pentacene crystals, we controlled the physical interactions at the semiconductor/gate dielectric (SiO₂) interface by inserting a hydrophobic self‐assembled monolayer (SAM, CH₃‐terminal) of organoalkyl‐silanes with an alkyl chain length of C8, C12, C16, or C18, as a complementary interlayer. We found that, depending on the physical structure of the dielectric surfaces, which was found to depend on the alkyl chain length of the SAM (ordered for C18 and disordered for C8), the pentacene nano‐layers in contact with the SAM could adopt two competing crystalline phases—a “thin‐film phase” and “bulk phase” – which affected the π‐conjugated nanostructures in the ultrathin and subsequently thick films. The field‐effect mobilities of the FET devices varied by more than a factor of 3 depending on the alkyl chain length of the SAM, reaching values as high as 0.6 cm² V^?1 s^?1 for the disordered SAM‐treated SiO₂ gate‐dielectric. This remarkable change in device performance can be explained by the production of well π‐conjugated and large crystal grains in the pentacene nanolayers formed on a disordered SAM surface. The enhanced electrical properties observed for systems with disordered SAMs can be attributed to the surfaces of these SAMs having fewer nucleation sites and a higher lateral diffusion rate of the first seeding pentacene molecules on the dielectric surfaces, due to the disordered and more mobile surface state of the short alkyl SAM.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.     

Organic Electronics: High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment (Adv. Funct. Mater. 16/2010)

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

Gate Capacitance‐Dependent Field‐Effect Mobility in Solution‐Processed Oxide Semiconductor Thin‐Film Transistors

Solution‐processed oxide semiconductors (OSs) used as channel layer have been presented as a solution to the demand for flexible, cheap, and transparent thin‐film transistors (TFTs). In order to produce high‐performance and long‐sustainable portable devices with the solution‐processed OS TFTs, the low‐operational voltage driving current is a key issue. Experimentally, increasing the gate‐insulator capacitances by high‐k dielectrics in the OS TFTs has significantly improved the field‐effect mobility of the OS TFTs. But, methodical examinations of how the field‐effect mobility depends on gate capacitance have not been presented yet. Here, a systematic analysis of the field‐effect mobility on the gate capacitances in the solution‐processed OS TFTs is presented, where the multiple‐trapping‐and‐release and hopping percolation mechanism are used to describe the electrical conductivity of the nanocrystalline and amorphous OSs, respectively. An intuitive single‐piece expression showing how the field‐effect mobility depends on gate capacitance is developed based on the aforementioned mechanisms. The field‐effect mobility, depending on the gate capacitances, of the fabricated ZnO and ZnSnO TFTs clearly follows the theoretical prediction. In addition, the way in which the gate insulator properties (e.g., gate capacitance or dielectric constant) affect the field‐effect mobility maximum in the nanocrystalline ZnO and amorphous ZnSnO TFTs are investigated.     

High-performance pentacene thin-film transistor with ZrLaO gate dielectric passivated by fluorine incorporation

Pentacene thin-film transistor with high-κ ZrLaO gate dielectric has been fabricated for the first time. After treating the dielectric in a fluorine plasma, the carrier mobility of the transistor can be greatly improved to 0.717 cm²/V s, which is more than 40 times that of one without plasma treatment. The major reasons should be larger pentacene grains and fewer traps in the device with gate dielectric passivated by the fluorine plasma. AFM confirms that relatively large and high pentacene islands form on the plasma-treated dielectrics in the initial growth stage, and the growth pattern obviously follows the Vollmer–Weber growth model. Furthermore, the surfaces of the dielectrics with different plasma treatment times are investigated by AFM, XPS and contact-angle measurement to reveal the mechanism/effects of the fluorine incorporation. Lastly, after exposure to atmosphere without encapsulation for 6 months, all the devices still display good transistor characteristics.     

High permittivity dielectrics for poly(3-alkylthiophene) field-effect transistor devices

In an attempt to disentangle the effects of permittivity and surface energy of the gate insulator (expressed by its dielectric constant k and water contact angle, respectively) on the performance of organic field-effect transistors (FETs), we fabricated top- and bottom-gate FET architectures with poly(3-alkylthiophenes) (P3ATs) of different side-chain lengths, using a range of gate dielectrics. We find that this class of semiconductor, including the short butyl-(C₄-) substituted derivative, is significantly less susceptible to the often detrimental effects that high-k dielectrics can have on the performance of many organic FETs. For bottom gate devices we identify the surface energy of the gate dielectric to predominantly dictate the device mobility.     

Highly Efficient Charge Transport in a Quasi‐Monolayer Semiconductor on Pure Polymer Dielectric

The study of monolayer organic field‐effect transistors (MOFETs) provides an effective way to investigate the intrinsic charge transport of semiconductors. To date, the research based on organic monolayers on polymeric dielectrics lays far behind that on inorganic dielectrics and the realization of a bulk‐like carrier mobility on pure polymer dielectrics is still a formidable challenge for MOFETs. Herein, a quasi‐monolayer coverage of pentacene film with orthorhombic phase is grown on the poly (amic acid) (PAA) dielectric layer. More significantly, charge density redistribution occurs at the interface between the pentacene and PAA caused by electron transfer from pentacene to the PAA dielectric layer, which is verified by theoretical simulations and experiments. As a consequence, an enhanced hole accumulation layer is formed and pentacene‐based MOFETs on pure polymer dielectrics exhibit bulk‐like carrier mobilities of up to 13.7 cm² V^?1 s^?1 from the saturation region at low V_GS, 9.1 cm² V^?1 s^?1 at high V_GS and 7.6 cm² V^?1 s^?1 from the linear region, which presents one of the best results of previously reported MOFETs so far and indicates that the monolayer semiconductor growing on pure polymer dielectric could produce highly efficient charge transport.     

High‐Speed,Low‐Voltage,and Environmentally Stable Operation of Electrochemically Gated Zinc Oxide Nanowire Field‐Effect Transistors

Single‐crystal, 1D nanostructures are well known for their high mobility electronic transport properties. Oxide‐nanowire field‐effect transistors (FETs) offer both high optical transparency and large mechanical conformability which are essential for flexible and transparent display applications. Whereas the “on‐currents” achieved with nanowire channel transistors are already sufficient to drive active matrix organic light emitting diode (AMOLED) displays; it is shown here that incorporation of electrochemical‐gating (EG) to nanowire electronics reduces the operation voltage to ≤2 V. This opens up new possibilities of realizing flexible, portable, transparent displays that are powered by thin film batteries. A composite solid polymer electrolyte (CSPE) is used to obtain all‐solid‐state FETs with outstanding performance; the field‐effect mobility, on/off current ratio, transconductance, and subthreshold slope of a typical ZnO single‐nanowire transistor are 62 cm²/Vs, 10⁷, 155 μS/μm and 115 mV/dec, respectively. Practical use of such electrochemically‐gated field‐effect transistor (EG FET) devices is supported by their long‐term stability in air. Moreover, due to the good conductivity (≈10^?2 S/cm) of the CSPE, sufficiently high switching speed of such EG FETs is attainable; a cut‐off frequency in excess of 100 kHz is measured for in‐plane FETs with large gate‐channel distance of >10 μm. Consequently, operation speeds above MHz can be envisaged for top‐gate transistor geometries with insulator thicknesses of a few hundreds of nanometers. The solid polymer electrolyte developed in this study has great potential in future device fabrication using all‐solution processed and high throughput techniques.     

The Effect of Interfacial Roughness on the Thin Film Morphology and Charge Transport of High‐Performance Polythiophenes

We control and vary the roughness of a dielectric upon which a high‐performance polymer semiconductor, poly(2,5‐bis(3‐alkylthiophen‐2‐yl)thieno[3,2‐b]thiophene) (pBTTT) is cast, to determine the effects of roughness on thin‐film microstructure and the performance of organic field‐effect transistors (OFETs). pBTTT forms large, well‐oriented terraced domains with high carrier mobility after it is cast upon flat, low‐surface‐energy substrates and heated to a mesophase. Upon dielectrics with root‐mean square (RMS) roughness greater than 0.5 nm, we find significant morphological changes in the pBTTT active layer and significant reductions in its charge carrier mobility. The pBTTT films on rough dielectrics exhibit significantly less order than those on smooth dielectrics through characterization with atomic force microscopy and X‐ray diffraction. This critical RMS roughness implies that there exists a condition at which the pBTTT domains no longer conform to the local nanometer‐scale curvature of the substrate.     

Self‐Assembled,Millimeter‐Sized TIPS‐Pentacene Spherulites Grown on Partially Crosslinked Polymer Gate Dielectric

Here, a highly crystalline and self‐assembled 6,13‐bis(triisopropylsilylethynyl) pentacene (TIPS‐Pentacene) thin films formed by simple spin‐coating for the fabrication of high‐performance solution‐processed organic field‐effect transistors (OFETs) are reported. Rather than using semiconducting organic small‐molecule–insulating polymer blends for an active layer of an organic transistor, TIPS‐Pentacene organic semiconductor is separately self‐assembled on partially crosslinked poly‐4‐vinylphenol:poly(melamine‐co‐formaldehyde) (PVP:PMF) gate dielectric, which results in a vertically segregated semiconductor‐dielectric film with millimeter‐sized spherulite‐crystalline morphology of TIPS‐Pentacene. The structural and electrical properties of TIPS‐Pentacene/PVP:PMF films have been studied using a combination of polarized optical microscopy, atomic force microscopy, 2D‐grazing incidence wide‐angle X‐ray scattering, and secondary ion mass spectrometry. It is finally demonstrated a high‐performance OFETs with a maximum hole mobility of 3.40 cm² V^?1 s^?1 which is, to the best of our knowledge, one of the highest mobility values for TIPS‐Pentacene OFETs fabricated using a conventional solution process. It is expected that this new deposition method would be applicable to other small molecular semiconductor–curable polymer gate dielectric systems for high‐performance organic electronic applications.     

Temperature‐Dependent Electrical Transport in Polymer‐Sorted Semiconducting Carbon Nanotube Networks

The temperature dependence of the electrical characteristics of field‐effect transistors (FETs) based on polymer‐sorted, large‐diameter semiconducting carbon nanotube networks is investigated. The temperature dependences of both the carrier mobility and the source‐drain current in the range of 78 K to 293 K indicate thermally activated, but non‐Arrhenius, charge transport. The hysteresis in the transfer characteristics of FETs shows a simultaneous reduction with decreasing temperature. The hysteresis appears to stem from screening of charges that are transferred from the carbon nanotubes to traps at the surface of the gate dielectric. The temperature dependence of sheet resistance of the carbon nanotube networks, extracted from FET characteristics at constant carrier concentration, specifies fluctuation‐induced tunneling as the mechanism responsible for charge transport, with an activation energy that is dependent on film thickness. Our study indicates inter‐tube tunneling to be the bottleneck and implicates the role of the polymer coating in influencing charge transport in polymer‐sorted carbon nanotube networks.     

Manipulating the Hysteresis in Poly(vinyl alcohol)‐Dielectric Organic Field‐Effect Transistors Toward Memory Elements

The origins of hysteresis in organic field‐effect transistors (OFETs) and its applications in organic memory devices is investigated. It is found that the orientations of the hydroxyl groups in poly(vinyl alcohol) (PVA) gate dielectrics are correlated with the hysteresis of transfer characteristics in pentacene‐based OFETs under the forward and backward scan. The applied gate bias partially aligns the orientations of the hydroxyl groups perpendicular to the substrate as characterized by reflective absorption Fourier transform infrared spectroscopy (RA‐FTIR), in which the field‐induced surface dipoles at the pentacene/PVA interface trap charges and cause the hysteresis. Treating PVA with an anhydrous solvent eliminates the residual moisture in the dielectrics layer, allowing for more effective control of the induced dipoles by the applied gate bias. OFETs of dehydrated‐PVA dielectrics present a pronounced shift of the threshold voltage (ΔV_Th) of 35.7 V in transfer characteristics, higher than that of 18.5 V for untreated devices and results in sufficient dynamic response for applications in memory elements. This work highlights the usage of non‐ferroelectric gate dielectrics to fabricate OFET memory elements by manipulating the molecular orientations in the dielectrics layer.     

Orders‐of‐Magnitude Reduction of the Contact Resistance in Short‐Channel Hot Embossed Organic Thin Film Transistors by Oxidative Treatment of Au‐Electrodes

In this study we report on the optimization of the contact resistance by surface treatment in short‐channel bottom‐contact OTFTs based on pentacene as semiconductor and SiO₂ as gate dielectric. The devices have been fabricated by means of nanoimprint lithography with channel lengths in the range of 0.3 μm < L < 3.0 μm. In order to reduce the contact resistance the Au source‐ and drain‐contacts were subjected to a special UV/ozone treatment, which induced the formation of a thin AuO_x layer. It turned out, that the treatment is very effective (i) in decreasing the hole‐injection barrier between Au and pentacene and (ii) in improving the morphology of pentacene on top of the Au contacts and thus reducing the access resistance of carriers to the channel. Contact resistance values as low as 80 Ω cm were achieved for gate voltages well above the threshold. In devices with untreated contacts, the charge carrier mobility shows a power‐law dependence on the channel length, which is closely related to the contact resistance and to the grain‐size of the pentacene crystallites. Devices with UV/ozone treated contacts of very low resistance, however, exhibit a charge carrier mobility in the range of 0.3 cm² V^–1 s^–1 < μ < 0.4 cm² V^–1 s^–1 independent of the channel length.     

Design of Novel Dielectric Surface Modifications for Perylene Thin‐Film Transistors

Dielectric surface modifications (DSMs) can improve the performance of organic thin‐film transistors (OTFTs) significantly. In order to gain a deeper understanding of this performance enhancement and to facilitate high‐mobility transistors, perylene based devices utilizing novel dielectric surface modifications have been produced. Novel DSMs, based on derivates of tridecyltrichlorosilane (TTS) with different functional end‐groups as well as polymeric dielectrics have been applied to tailor the adhesion energy of perylene. The resulting samples were characterized by electronic transport measurements, scanning probe microscopy, and X‐ray diffraction (XRD). Measurements of the surface free energy of the modified dielectric enabled the calculation of the adhesion energy of perylene upon these novel DSMs by the equation‐of‐state approach. These calculations demonstrate the successful tailoring of the adhesion energy. With these novel DSMs, perylene thin‐films with a superior film quality were produced, which enabled high‐performance perylene‐based OTFTs with high charge‐carrier mobility.     

High‐Mobility and Low Turn‐On Voltage n‐Channel OTFTs Based on a Solution‐Processable Derivative of Naphthalene Bisimide

In organic electronics solution‐processable n‐channel field‐effect transistors (FETs) matching the parameters of the best p‐channel FETs are needed. Progress toward the fabrication of such devices is strongly impeded by a limited number of suitable organic semiconductors as well as by the lack of processing techniques that enable strict control of the supramolecular organization in the deposited layer. Here, the use of N,N′‐bis(4‐n‐butylphenyl)‐1,4,5,8‐naphthalenetetracarboxylic‐1,4:5,8‐bisimide (NBI‐4‐n‐BuPh) for fabrication of n‐channel FETs is described. The unidirectionally oriented crystalline layers of NBI‐4‐n‐BuPh are obtained by the zone‐casting method under ambient conditions. Due to the bottom‐contact, top‐gate configuration used, the gate dielectric, Parylene C, also acts as a protective layer. This, together with a sufficiently low LUMO level of NBI‐4‐n‐BuPh allows the fabrication and operation of these novel n‐channel transistors under ambient conditions. The high order of the NBI‐4‐n‐BuPh molecules in the zone‐cast layer and high purity of the gate dielectric yield good performance of the transistors.