3dB带状线电桥的研究与设计

首先对90°电桥进行了分析。提出一种特殊结构的宽带3dB电桥的设计方案。该方案可使电桥方向性更好、制作工艺更加简便,其带宽可达到9～11GHz,可以承受较大的功率容量,体积小,新式结构使其实现了低插损、高方向性和宽频带,并且易生产、易调试。实测结果和仿真结果基本吻合,验证了研究结果的一致性。     

一种新型宽带平面和差网络

提出了一种新型的基于环形电桥结构的宽带平面和差网络。首先提出了一种新型的宽带微带/槽线转换结构,然后将该结构引入到传统的环形电桥结构中,优化设计了一种改进型环形电桥,最后采用四个改进的环形电桥构建了双平面和差网络。测试结果表明:在4.05～7.425GHz的频率范围内,八个端口的驻波均小于2,输入端口之间的隔离度均在20dB以上,输出端口之间的隔离度大于30dB,和端口的插入损耗小于0.5dB,差端口的零值深度小于-30dB。该和差网络具有性能优良、结构简单、制作成本低等优点,在宽频带单脉冲雷达天馈系统中得到了成功的应用。     

X波段宽带圆极化微带天线的设计与仿真

设计并仿真了一种在X波段工作的宽带圆极化微带天线,其结构为双层介质与空气结合,通过宽带环形电桥和W ilkinson功分器馈电,可使天线驻波带宽达83%,3dB轴比带宽达75%。     

一种新型的毫米波功率合成电路

针对毫米波功率合成技术研究,吸取传统W ilk inson电桥的优点,提出了一种新型低损耗毫米波微带集成3dB电桥,其成本低、加工制作容易、在32GHz~37GHz,插损为0.2dB;以此3dB电桥为基础的Ka频段功率合成网络,在频率33~35GHz,合成效率达75%.     

S频段宽带3dB定向耦合器的设计

介绍了用宽边耦合来实现的2～3GHz、耦合度为3dB的宽带带状线定向耦合器,提出一种改进的宽带3dB电桥的设计方案,这种电桥具有体积小,差损低,稳定性好以及易于生产、调试的优点。利用HFSS软件进行优化设计,最终实测结果和仿真结果基本吻合,验证了研究结果的一致性。     

可收拢展开的宽带双圆极化柔性薄膜天线

星载相控阵雷达因其平台的特殊性要求其天线具有大型轻质、可收拢展开的特点。设计了一种可收拢展开的宽带双圆极化柔性薄膜天线。天线各层均采用柔性薄膜材料制作,相邻层间为空气,因此天线整体为柔性可收拢展开。采用两相互垂直的"H"形缝隙和双层微带贴片结构,并结合3 dB电桥实现了宽带和高隔离度的双圆极化。仿真和测试结果表明,该薄膜天线单元两馈电端口驻波小于2的相对带宽约为36%,极化隔离度大于32 dB,并给出了天线单元双圆极化波瓣方向图的测试结果,其3 dB波瓣宽度为64°,天线单元增益为6.2 dB,并设计了天线小阵。     

新型3 dB电桥的设计

针对450 MHz频段通信系统中3 dB电桥体积过大的情况,基于微波网络理论提出了一种方形微带线3 dB电桥实现方案.借助Agilent公司的ADS(Advanced Design System)软件完成了仿真设计,通过其内嵌的LAYOUT工具并结合PADS LAYOUT软件,设计制作了PCB版电路.实测结果接近仿真数据,各端口回波损耗低于-20 dB,端口间隔离小于-30 dB,均满足450 MHz中频、20 MHz带宽前馈线性功放模组的要求,而其版图面积只有传统环形电桥版图面积的8%.     

宽带射频电桥的设计及实现

设计了基于同轴巴伦传输线的宽带射频电桥,此电桥采用套有磁环的同轴传输线完成单端信号到差分信号的转换,设计了包含测试端口及隔离端口的电桥,并将差分信号加载到电桥以完成传输信号与反射信号分离,利用FR4板材制作了电桥并完成各类指标测试。测试结果表明,该电桥最高工作频率约为 3ＧＨｚ,方向性约为10ｄＢ＠1.5ＧＨｚ,插入损耗最大约为3.5ｄＢ,可广泛应用到各类通信及测试系统中。     

K波段单平衡上变频器的设计

文中介绍了一种应用于宽带无线接入系统发射机的K波段单平衡上变频器的设计方法,并给出了仿真结果和电路版图。电路选用Alpha公司的砷化镓肖特基势垒二极管,采用易于实现的环形电桥结构。通过在环形电桥的一个端口附加45。相移实现了上边带单平衡混频,变频损耗小于6dB,三阶交调系数为39dB,输入1dB压缩点为10dBm。整个电路具有低成本、低变频损耗的特点。     

3dB电桥建模技术

本文从设计一种LTCC结构的3dB／900电桥出发，简述了其设计方法，并介绍了在Ansoft HFSS软件中设计好的且通过LTCC工艺制作已达到合格指标的电桥在Agilent ADS电路仿真软件中建立一个器件模型，即电桥的一种建模技术，以便这种电桥能和其它电路集成在一起形成更复杂的微波模块。     

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $Sigma Delta$ Modulator

Although SigmaDelta modulators have largely been implemented as discrete-time (DT) circuits, a continuous-time (CT) approach offers significant advantages for realizing high-accuracy A/D converters at signal bandwidths where technology considerations may impose significant constraints. A CT design allows for relaxed amplifier unity-gain frequency and power requirements, which can enable the realization of high-resolution modulators with bandwidths of several MHz or more at low power. It also provides the advantage of inherent anti-aliasing filtering. This paper introduces a hybrid CT/DT SigmaDelta modulator for A/D conversion that combines the benefits of CT and DT circuits, while mitigating the challenges associated with CT design. The second-order first stage of a two-stage cascade is implemented in CT, while the first-order second stage is a DT circuit. An experimental prototype of the proposed modulator, integrated in 0.18-mum CMOS technology, operates from a 1.2-V analog supply to allow for easier migration to a 0.13-mum or 90-nm CMOS technology. The prototype achieves a dynamic range of 77 dB, a peak SNR of 71 dB, a peak SNDR of 67 dB, and worst-case anti-aliasing filtering of 48 dB for a signal bandwidth of 7.5 MHz and a sampling rate of 240 MHz. The total power dissipation is 89 mW, including 63.6 mW of analog power.     

Omnidirectional transmitter combining antenna

Historically, it has been difficult to combine transmitters which are closely spaced in frequency onto the same omnidirectional antenna. Two principal techniques have been used: cavity combining and transmission line hybrid combining. When using cavities, the minimum separation is limited by the amount of insertion loss that is acceptable and by the frequency stability of the cavities. In the 800- MHz land mobile frequency band, cavity combining has been used to combine transmitters as closely spaced as 0.5 MHz with 3 dB of insertion loss. When combining transmitters separated less than 0.5 MHz, hybrid combining has been used. When two transmitters are combined using this technique, half of the power of each is dissipated into a matched load. Further, each time the number of transmitters being combined is doubled, an additional 3 dB is added to the insertion loss. A new technique has been developed which utilizes transmission line hybrids to combine the transmitters, but which does not suffer from large insertion loss. The power that was previously dissipated in the resistive load is radiated in a manner that produces an omnidirectional pattern. The antenna and network that accomplish this combine signals with 90° phase shifts. Measurements show that it is possible to combine eight transmitters arbitrarily close in frequency with 35 dB of isolation between adjacent channels, less than 0.5 dB insertion loss, and with horizontal pattern circularity better than ±3 dB. Additionally, this technique can be combined with cavity combining to maintain high isolation between additional tranmitters.     

Rayleigh-wave delay line using two grating-array transducers at 2.55 GHz

Grating-array transducers are used to launch acoustic surface waves at 2.55 GHz on a LiNbO3 substrate. The insertion loss of a 1.5 ?s delay line is equal to 39 dB with matching stubs at input and output. The 3 dB bandwidth is equal to 87 MHz. For this frequency range, array transducers are easier to fabricate than standard interdigital transducers. Performances of the two types of transducers are compared.     

连续时间型ΣΔ调制器的系统级设计和建模方法

采用冲激不变法把z域环路滤波器变换到s域,并对连续时间型ΣΔ调制器设计中的非理想因素进行系统级建模和仿真。基于低功耗设计考虑,调制器采用有源-无源混合型环路滤波器,并通过离散时间微分技术移除信号求和模块。设计实例实现了一个五阶3-bit连续时间型ΣΔ调制器,采用SMIC0.18μm1P6M标准CMOS工艺验证。芯片工作在1.8V电源电压和128MHz时钟频率,在1MHz的信号带宽内,调制器的动态范围为84dB,峰值SNR和SNDR分别为80dB和78dB,功耗为9mW。测试结果验证了设计技术和建模方法。     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

Design of a 2-pole LTCC filter for wireless communications

This letter outlines the designing and manufacture of a miniaturized bandpass filter realized by low-temperature cofired ceramic (LTCC) technology for wireless products. The bandpass filter with a central frequency of 1950 MHz and a 5% passband is designed as a three-dimensional (3-D) structure based on lumped components. The design technique based on cascading overall circuit into blocks and computer-aided design of electrical circuit is presented. Experimental measurements were compared with modeling. The insertion losses in the passband (100 MHz) were less than 2 dB and the attenuation more than 20 dB in the stopband. The area occupied by the filter is 6.6/spl times/6.6/spl times/0.836 mm/sup 3/ in plane.     

400 Mbit/s Digital Repeater Circuitry Provided by a New Design Method and Beam Lead GHz Transistors

A stable, compact, and high-performance regenerative repeater circuitry, suitable for digital transmission systems up to several hundred Mbit/s, has been provided through utilization of new devices, such as 7 GHz beam lead shielded junction transistors, and through a new computer-aided design method, and has been successfully applied to the 400 Mbit/s experimental coaxial cable PCM system. Major features of this repeater circuitry are: (1) an equalizing amplifier with low noise figure (7.6 dB), small intersymbol interference (12%), and automatic line equalization of 21 dB tracking range at 200 MHz; (2) a regenerative output circuit with bipolar pulses of 2.4 Vop amplitude and 700 ps rise time; and (3) total performance with sufficient noise margin (10 dB for error rate 10^-11over a line of 56 dB loss at 200 MHz), small static pattern jitter (20°pp), smaller size (270 times 160 times 52mm), and lower power (5.8 W). These have been achieved by use of: (1) new devices such as beam lead transistors with fTof 7 GHz,Leof 0.2 nH andCobof 0.4 pF and tantalum thin film hybrid integrated circuits; and (2) a new CAD system including block simulation, network design/ simulation, layout design subsystems which use transmission quality (error rate and jitter) as a design criterion, and which can also be directly connected to the manufacture automation systems, e.g., for mask preparation, and transistor mounting by bonding.     

一种线性相位LC滤波器的设计

为解决滤波器带外抑制和通带内相位波动之间的矛盾,该文介绍了一种线性相位LC滤波器的设计方法,通过对滤波器传输零点特性进行分析,根据指标要求灵活设计电路拓扑结构和零点位置,采用内、外均衡电路级联网络两种方法,来实现具有高矩形、线性相位特性的滤波器。设计了中心频率21.4 MHz、0.5 dB带宽大于10 MHz、矩形系数(45 dB/0.5 dB)小于2、带内相位波动绝对值小于5°和中心频率1 300 MHz、1 dB带宽大于200 MHz、矩形系数(35 dB/1 dB)小于2、带内相位波动绝对值小于5°两款滤波器。该方法工程实用化强,便于调试和制作,可应用于幅相特性要求高的微波系统中,提高了系统性能指标。     

LTCC基P波段90°功分器的制作

文章以LTCC基P波段90°功分器的设计和制作为例,从无源设计仿真和LTCC工艺阐述了P波段功分器的研制过程。选用了承受功率大、尺寸相对较小的宽边耦合器结构。设计的宽边耦合器采用多层结构,有利于发挥LTCC基板多层、高集成度等优点。其电路物理模型为Broadside-coupled symmetric stripline（BCL）,采用的介质为LTCC,介电常数为5．9,每层介质厚度为0．1mm,导体采用Ag浆。在实物制作过程中,TOP层和Bottom层是采用灌银通孔实现的。最终测试结果与仿真结果吻合较好,在225MHz～400MHz频段内隔离23dB,插损0．5dB,驻波1．1,相平衡度±2．5,功率250W．