Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk has become a major bottleneck for design closure. The effectiveness of traditional buffering and spacing techniques for noise reduction is constrained by the limited available resources on chip. In this paper, we present a method for incorporating crosstalk reduction criteria into global routing under a broad power supply network paradigm. This method utilizes power/ground wires as shields between signal wires to reduce capacitive coupling, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's metric, and our work demonstrates, for the first time, that this metric shows good fidelity on average. An effective noise margin inflation technique is also proposed to compensate for the pessimism of Devgan's metric. Experimental results on testcases with up to about 10000 nets point towards an asymptotic runtime that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion or only shield insertion after buffer planning.     

A DLL-Based Variable-Phase Clock Buffer

A variable-phase clock buffer that uses a delay-locked loop (DLL) is presented. The variable-phase clock is achieved by switching the multiphase outputs of the divider in the DLL. The output phase is adjustable in a step of where pi/n is the ratio of two voltage-controlled delay lines in the proposed circuit. The prototype has been fabricated in a 0.18- CMOS process to realize the output phases of 0deg, 90deg, 180deg, and 270deg. The corresponding measured phase error is 3.24deg, 3.46deg, 3.89deg, and 1.94deg, respectively. The measured root-mean-squared jitter is 1.81 ps. The clock buffer consumes 67 mW including I/O circuits from a single 1.8-V supply at 600 MHz.     

V4系列FPGA全局时钟缓冲器的内建自测试研究

提出一种新的基于V4系列FPGA全局时钟缓冲器的内建自测试方法。目前关键时钟缓冲器内建自测试正面临巨大的挑战,时序问题是目前发现的时钟缓冲器内建自测试的主要问题。由于时钟缓冲器输入端的同步开关会产生不同的相移,使得正常的器件内建自测试中产生故障指示。此外,目前时钟缓冲器内建自测试使用的是普通的布线资源连接时钟信号,而不是使用专用的时钟布线资源,这种方法会加剧时序问题。提出一种改良的方法去解决内建自测试的时序问题,并讨论这种方法对于可测试的最大时钟频率和总测试时间的影响。所有测试环节均在V4系列FPGA上实现。     

一款高性能时钟驱动器电路的设计

时钟器件芯片可以实现通信网定时同步、时钟产生、时钟恢复和抖动滤除、频率合成和转换、时钟分发和驱动等功能。在系统设计中,选用好的时钟驱动芯片,可以省去系统时钟树设计,既节省空间,又提高系统性能。介绍一款高性能时钟驱动器的集成电路设计方法,主要性能要求有:低传播延时、低输出偏斜、低输出抖动、抗电磁干扰能力、抗ESD能力,一一详述了达到各项要求的设计。     

一种层次式加载BUFFER的时钟网布线

多级时钟树构造是解决时钟布线问题的关键。本文提出一种新的层次式布线策略,它将拓扑生成,绕障碍ＤＭＥ及ＢＵＦＦＥＲ定位同时进行考虑,避免了布线的盲目性,减少了后处理工作。首先,对时钟汇点进行层次式均匀划分,在各个局域区域同时进行时钟子树的拓扑生成和ＤＭＥ嵌入;     

Legitimate Skew Clock Routing with Buffer Insertion

In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective. Xinjie Wei received his B.Sc. degree in Computer Science from the PLA Nanjing Institute of Communications Engineering in 1993, and got M.S. degree in Computer Science from Xidian University in 1998. He is currently pursuing the Ph.D. degree at Tsinghua University. His research interests include computer network security, neural network and design automation for VLSI circuits and systems. And the major research attention is focused on VLSI physical design. Yici Cai received BSc degree in Electronic Engineering from Tsinghua University in 1983 and received in and MS degree in Computer Science & Technology from Tsinghua University in 1986, She has been an associate professor in the Department of Computer Science & Technology, Tsinghua University. Beijing, China. Her research interests include VLSI layout theory and algorithms. Meng Zhao has been an researcher in Semiconductor Industry Association of Beijing. She received her Bachelor of Engineering degree in Electronical Engineering from Tsinghua University, China, in 2000. She received her Master of Science degree in Computer Science from Tsinghua University, China, in 2003. Her research interests include VLSI design and CAD, Electronical material and device, VLSI verification and so on. Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. Since 1988, he has been a professor in the Department of Computer Science Technology, Tsinghua University. His research interests include VLSI layout algorithms and DA systems. He is the fellow of IEEE and the Senior Member of Chinese Institute of Electronics.     

Pulse Suppression Technique for Mitigating Digital Clock Noise

A practical digital clock noise mitigation technique based on pulse removal is presented. Clock frequency is increased to generate an excess pulse, which is removed in order to match the number of pulses in an average time frame. The location of the excess pulse is selected as the same time point or randomly selected in every time frame. Mathematical analyses are presented for both methods. The circuit is implemented using a state machine on a FPGA. Measurement results indicate more than 40 dB improvement on the digital noise level within a band of interest.     

Clock Skew Optimization for Peak Current Reduction

The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that, for a given clock cycle time, determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern.     

Common-Mode Noise Reduction for Power Factor Correction Circuit With Parasitic Capacitance Cancellation

In this paper, a method using negative capacitance to cancel the common-mode (CM) parasitic capacitance of boost power factor correction (PFC) converters is proposed. Both the theoretical analysis and experiments show that the proposed method is very easy to implement and very efficient to reduce CM noise.     

Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. This paper introduces both a novel on-chip decoupling capacitance methodology and active noise cancellation (ANC) structure. The decoupling methodology focuses on quantification and location. The ANC structure, with an area of 50 $mu {hbox {m}} times,55 mu{hbox {m}}$, uses decoupling capacitance to sense noise and inject a proportional current into $V _{rm SS}$ as a method of reduction. A chip has been designed and fabricated using TSMC's 90-nm technology. Measurements show that the decoupling methodology improved the average voltage headroom loss by 17% while the ANC structure improved the average voltage headroom loss by 18%.      

NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach

Supply voltage assignment (SVA) can alleviate the performance aging induced by the negative bias temperature instability (NBTI) effect. However, due to the random characteristic of an actual system workload, it is difficult to estimate the aging rate and control the supply voltage reasonably. To solve this problem, we present a workload-aware SVA method (WSVA) that encapsulates the workload change into the aging estimation using an LUT-based approach. Moreover, an NBTI and leakage co-optimization strategy based on an integer linear programming (ILP) approach is proposed to obtain the optimal input vector in standby mode. Simulation experiments on multiple benchmark circuits demonstrate that the LUT-based approach can track the dynamic change of the workload online and provide an accurate aging estimate for SVA with little computation cost. Compared with the SVA method without considering the workload, the proposed aging estimation approach and the optimal input vector selection strategy in the WSVA framework can enable the CMOS circuit conserve additional power dissipation while guaranteeing the performance requirements.     

An LC-Based Clock Buffer With Tunable Injection Locking

This paper introduces a hybridized version of two common topologies of LC-based clock buffers. The proposed design can minimize jitter by adaptively adjusting the ratio between these two topologies. The analysis shows that the setting for optimum jitter depends on the relative level between the input noise and the inherent noise of the clock buffer. The long-term and short-term jitters are both studied and supported by measurement. A frequency tuning technique based on a voltage-swing digitizer is also demonstrated. The test chip is fabricated in a 1P8M 1.2-V 0.13-$mu$m digital CMOS process. The power consumption of the proposed LC-based clock buffer is 12 mW.      

配电房噪声频率分布特性仿真分析与治理

针对居民区配电房噪声扰民目前没有有效解决手段的问题,分析了配电房噪声的产生原因及频率分布特性,对比分析了噪声计算方法的优缺点,并利用COMSOL软件对配电房噪声进行了仿真计算,提出了一种利用复合阻尼材料降低配电房噪声的新思路。     

Design and Validation of a Power Supply Noise Reduction Technique

For the high-performance microprocessors with high-bandwidth I/O, the power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high-quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). In this paper, we will present two implementations of an approach of using on-die resistors in series with the package capacitance to dampen the high-frequency noise. We will show by validation on the 90-nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings. The results of several validation experiments, including the measurement of noise and impedance of the I/O power delivery, and the post-layout simulation will also be presented.     

一种适用于相变存储器的低噪声时钟发生器

基于相变存储器的特性,设计了一种具有低功耗、低噪声的时钟发生器.该时钟由压控振荡器产生,并通过时钟控制电路转换为相变存储器存储操作所需的reset、set信号.由于纳米尺寸下的相变存储器件受噪声影响严重,该电路降低了外围驱动对相变存储单元的低频噪声干扰,能够改进相变存储器性能.电路采用40 nm CMOS工艺设计,电源电压为1.8V,功耗为1.26 mW,RMS抖动为0.83 ps,p-p抖动为5.14 ps,芯片面积为80 μm×90 μm.     

一种加载缓冲器的有界偏差平面时钟布线算法

提出了一种加载缓冲器的有界偏差平面时钟布线方法.该方法由两步组成:第一步,由平面时钟布线生成一个时延相对平衡的平面时钟树;第二步,通过在平面时钟树的适当位置插入缓冲器,得到一个有界时钟偏差的平面时钟树.     

Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise

Increased buffer insertion along on-chip global lines and growing amounts of leakage power have resulted in buffer-based leakage emerging as one of the chief contributors to system leakage power. In this paper, a bus system prototype is implemented in an industrial 65-nm SOI technology and measured results show up to a 45% reduction in total bus system power and an average reduction of 2.4$times$ in standby mode leakage power.      

Noise Adaptive Fuzzy Switching Median Filter for Salt-and-Pepper Noise Reduction

This letter presents a novel two-stage noise adaptive fuzzy switching median (NAFSM) filter for salt-and-pepper noise detection and removal. Initially, the detection stage will utilize the histogram of the corrupted image to identify noise pixels. These detected “noise pixels” will then be subjected to the second stage of the filtering action, while “noise-free pixels” are retained and left unprocessed. Then, the NAFSM filtering mechanism employs fuzzy reasoning to handle uncertainty present in the extracted local information as introduced by noise. Simulation results indicate that the NAFSM is able to outperform some of the salt-and-pepper noise filters existing in literature.      

All Digital Spread Spectrum Clock Generator for EMI Reduction

An effective solution to control electromagnetic interference in computing appliances such as DVD players or home theater systems is to apply modulation on the system clock. The presence of modulation on the clock reduces the radiated power per unit bandwidth. We present the implementation of a spread spectrum clock generator (SSCG) using strictly digital components. A digital delay line (DDLi) controlled by a small digital circuit is used to increase or decrease the delay on a clock and hence create a modulated output. The DDLi total electrical length is no longer than one period of the 27-MHz reference clock as the digital circuit can adjust to the limited length of the line. The circuit can produce up or down spread by modulating the frequency of the reference with a triangular waveform. The measured peak power reduction is greater than 13 dB for a deviation of about 3% and a frequency modulation of 100 kHz. A real-time digital calibration circuit enables a process and temperature independent operation. The circuit occupies 0.06 mm² in a 0.15-mum CMOS process and consumes 7.1 mW     

原子钟噪声的多尺度分形特征

将小波分析理论和分形理论结合起来，讨论原子钟噪声的多尺度分形特征。文中研究结果表明，在大尺度上，原子钟噪声具有某种以周期变化；在小尺度上，原子钟噪声是完全随机的变化特征。