A Graph-Based Approach to Power-Constrained SOC Test Scheduling

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.     

An exploration of aggregation convergecast scheduling

We consider the problem of aggregation convergecast scheduling as it applies to wireless networks. The solution to aggregation convergecast satisfies the aggregation process, expressed as precedence constraints, combined with the impact of the shared wireless medium, expressed as resource constraints. Both sets of constraints influence the routing and scheduling. We propose an aggregation tree construction suitable for aggregation convergecast that is a synthesis of a tree tailored to precedence constraints and another tree tailored to resource constraints. Additionally, we show that the scheduling component can be modeled as a mixed graph coloring problem. Specifically, the extended conflict graph is introduced, and through it, a mapping from aggregation convergecast to mixed graphs is described. In the mixed graph, arcs represent the precedence constraints and edges represent the resource constraints. The mixed graph chromatic number corresponds to the optimal schedule length. Bounds for the graph coloring are provided and a branch-and-bound strategy is subsequently developed from which we derive numerical results that allow a comparison against the current state-of-the-art heuristic.     

Scheduling of uniform multidimensional systems under resourceconstraints

Multidimensional (MD) systems are widely used to model scientific applications such as image processing, geophysical signal processing, and fluid dynamics. Such systems, usually, contain repetitive groups of operations represented by nested loops. The optimization of such loops, considering processing resource constraints, is required in order to improve their computational time. Most of the existing static scheduling mechanisms, used in the high-level synthesis of very large scale integration (VLSI) architectures, do not consider the parallelism inherent to the multidimensional characteristics of the problem. This paper explores the basic properties of MD loop pipelining and presents two novel techniques, multidimensional rotation scheduling and push-up scheduling, able to achieve the shortest possible schedule length. These new techniques transform a multidimensional data flow graph representing the problem, while assigning the loop operations to a schedule table. The multidimensional rotation scheduling is an iterative “heuristic” method, depending upon user input, while the push-up scheduling algorithm is able to compute the new schedule in polynomial time. The optimal resulting schedule length and the efficiency of the algorithms are demonstrated by a series of practical experiments     

Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.     

Resource-constrained loop list scheduler for DSP algorithms

We present a new algorithm for resource-constrained scheduling for digital signal processing (DSP) applications when the number of processors is fixed and the objective is to obtain a schedule with the minimum iteration period. This type of scheduling is best suited for moderate speed applications where conservation of area and power is more important than speed. We define and make use of newgraph dependent constraints to obtain a lower bound estimate on the iteration period for any data-flow graph. By satisfying these constraints before performing the scheduling task, we can restrict the design space and can generate valid schedules in less time than previously reported. The graph dependent constraints provide a more accurate lower bound estimate on the iteration period than previously published results. This new scheduling algorithm exploits the iterative nature of DSP algorithms and uses aniterative-loop based scheduling approach. This resource scheduling algorithm has been incorporated in the Minnesota ARchitecture Synthesis (MARS) system. Our approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining to generate optimal and near optimal schedules.This research was supported by the Advanced Research Projects Agency under grant number F33615-93-C-1309 and the office of Naval Research under contract number N00014-91-J-1008.     

Efficient variable partitioning and scheduling for DSP processors with multiple memory modules

Multiple on-chip memory modules are attractive to many high-performance digital signal processing (DSP) applications. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. However, making effective use of multiple memory modules remains difficult. The performance gain in this kind of architecture strongly depends on variable partitioning and scheduling techniques. In this paper, we propose a graph model known as the variable independence graph (VIG) and algorithms to tackle the variable partitioning problem. Our results show that VIG is more effective than interference graph for solving variable partitioning problem. Then, we present a scheduling algorithm known as the rotation scheduling with variable repartition (RSVR) to improve the schedule lengths efficiently on a multiple memory module architecture. This algorithm adjusts the variable partitions during scheduling and generates a compact schedule based on retiming and software pipelining. The experimental results show that the average improvement on schedule lengths is 44.8% by using RSVR with VIG. We also propose a design space exploration algorithm using RSVR to find the minimum number of memory modules and functional units satisfying a schedule length requirement. The algorithm produces more feasible solutions with equal or fewer number of functional units compared with the method using interference graph.     

Maximizing the Network Stability in Mobile WiMAX Mesh Networks

Resource scheduling and routing tree construction in WiMAX mesh centralized scheduling are not defined in the standard and thus are subject to extensive research. In this paper, we consider routing and scheduling in a WiMAX-based mesh network. We assume that nodes are not necessarily stationary, but rather mobile with a mobility that may yield to frequent topology changes (e.g., failure of existing links and creation of new transmission links). We model the joint routing and scheduling as an optimization problem whose objective is either to determine a minimum length schedule by maximizing spectrum spatial reuse or maximizing the network lifetime by routing around the less stable RF-links, while satisfying a set of (uplink/downlink) end-to-end demands. While solving the problem with the two objectives, we study the tradeoffs between these two objectives. We show that minimizing the schedule length forces the joint routing and scheduling problem to generate a routing tree and feasible transmission groups which favor higher spectrum spatial reuse (and hence higher system throughput), irrespective of the robustness of the selected transmission links. In addition, we show that maximizing the network stability or lifetime yields the selection of different routing trees and slot assignments which do not necessarily result in shorter schedule length. We perform numerical experiences where we compare the performances of our proposed models with respect to the network stability and resource spatial reuse.     

Joint scheduling and routing using space–time graphs for TDM wireless mesh networks

This paper presents a novel algorithm for joint routing and scheduling in TDM wireless mesh networks. We introduce a new construct, called a “space–time graph,” which incorporates the spatial and temporal aspects of routing in one structure by replicating a spatial network connectivity graph in layers along the time dimension. The power of the space–time graph lies in the fact that a path from one node to another in it specifies both a physical route in space as well as a schedule in time for a message. Hence the complicated and intractable problem of routing and scheduling reduces to the relatively simpler problem of determining shortest paths in a graph. Through simulations we show that a simply greedy algorithm on the space–time graph outperforms two state-of-the-art methods in terms of time taken to successfully transmit a set of messages from their sources to their destinations.     

Optimum Integrated Link Scheduling and Power Control for Multihop Wireless Networks

In this paper, a new mathematical programming formulation is developed for minimizing the schedule length in multihop wireless networks based on the optimal joint scheduling of transmissions across multi-access communication links and the allocation of transmit power levels while meeting the requirements on the signal-to-interference-plus-noise ratio at intended receivers. The authors prove that the problem can be represented as a mixed-integer linear programming (MILP) and show that the latter yields a solution that consists of transmit power levels that are "strongly Pareto optimal". It was demonstrated that the MILP formulation can be used effectively to derive optimal scheduling and power levels for networks with as many as 30 designated communication links. The authors show that the MILP formulation can also be effectively solved to provide upper and lower bounds (corresponding to an approximation factor Delta) for the optimum schedule length of networks with as many as 100 designated links. It is proved that the integrated link scheduling and power control problem (ILSP) is NP-complete. Consequently, a heuristic algorithm of polynomial complexity is developed and investigated for solving the problem in a timely and practical manner. The algorithm is based on the properties of a novel interference graph, i.e., the "generalized power-based interference graph", whose "chromatic" and "independence numbers" provide fundamental bounds for the ILSP. It is demonstrated that the frame length of schedules realized by the heuristic scheme resides in the 25th percentile of those attained by the optimal mechanism for randomly generated topologies with as many as 30 designated communication links. Furthermore, it is shown that the algorithm significantly outperforms a corresponding algorithm presented in the literature     

Scheduling Tests for 3D Stacked Chips under Power Constraints

This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.     

A genetic algorithm approach to a general category projectscheduling problem

A genetic algorithm (GA) approach is proposed for the general resource-constrained project scheduling model, in which activities may be executed in more than one operating mode, and renewable as well as nonrenewable resource constraints exist. Each activity's operation mode has a different duration and requires different amounts of renewable and nonrenewable resources. The objective is the minimization of the project duration or makespan. The problem under consideration is known to be one of the most difficult scheduling problems, and it is hard to find a feasible solution for such a problem, let alone the optimal one. The GA approach described in this paper incorporates problem-specific scheduling knowledge by an indirect chromosome encoding that consists of selected activity operating modes and an ordered set of scheduling rules. The scheduling rules in the chromosome are used in an iterative scheduling algorithm that constructs the schedule resulting from the chromosome. The proposed GA is denoted a hybrid GA (HGA) approach, since it is integrated with traditional scheduling tools and expertise specifically developed for the general resource-constrained project scheduling problem. The results demonstrate that HGA approach produces near-optimal solutions within a reasonable amount of computation time     

Scheduling switching element (SE) disjoint connections instage-controlled photonic banyans

We study the problem of scheduling switching element (SE)-disjoint connections in banyans and dilated banyans under stage control and show how it applies to photonic cross-connect (or switch) technology. For a given set of connections (or packets), it is desirable to establish them in as few rounds as possible where the number of rounds (i.e., schedule length) corresponds to the degree at which a cross-connect may be multiplexed in time or wavelength. For a stage-controlled banyan, three scheduling algorithms are described. The first two algorithms perform well when the number of connections to be scheduled is small and large, respectively, but perform poorly otherwise. The third algorithm is optimal in that it can generate a schedule of minimum length with a polynomial time complexity. We determine the average schedule length in a banyan using these three algorithms through both analysis and simulation and extend our analysis to dilated banyans     

Power-efficient and interference-free link scheduling algorithms for connected wireless sensor networks

A fundamental aspect in performance engineering of wireless sensor networks (WSN) is optimizing the set of links that can be concurrently activated to meet a given signal-to-interference-plus-noise ratio (SINR) threshold. The solution of this combinatorial problem is a key element in wireless link scheduling. Another key architectural goal in WSN is connectivity. The connectivity of sensor nodes is critical for WSN, as connected graphs can be used for both data collection and data dissemination. In this paper, we investigate the joint scheduling and connectivity problem in WSN assuming the SINR model. We propose algorithms to build connected communication graphs with power-efficient links to be scheduled simultaneously in one time slot. The algorithms aiming at minimizing the number of time slots needed to successfully schedule all the given links such that the nodes can communicate without interference in the SINR model. While power-efficient and interference-free schedules reduce energy consumption, minimization of the schedule length (shortest link scheduling) has the effect of maximizing network throughput. We propose one greedy randomized constructive heuristic, two local search procedures, and three greedy randomized adaptive search procedures metaheuristics. We report computational experiments comparing the effectiveness of the proposed algorithms. Our simulation also shows the trade-off between power consumption and schedule length and the results indicate that not only the overall performance of our algorithms, but also show that the total power and schedule length value of its solutions are better than the existing work.

     

Aggregation convergecast scheduling in wireless sensor networks

We consider the problem of scheduling in wireless sensor networks for the purposes of aggregation convergecast. We observe that existing schemes adopt essentially a two phase approach, consisting of, first, a tree construction and, second, a scheduling phase. Following a similar approach, we propose two new improvements, one to each of the two phases. Starting with a new lower bound on the schedule length, we make use of it in the tree construction phase. The tree construction phase consists of solutions to instances of bipartite graph semi-matchings. The scheduling phase is a weight-based priority scheme that obeys dependency (tree) and interference constraints. Our extensive experiments show that, overall, our proposed solution not only outperforms all previously proposed solutions in terms of schedule length, but it also significantly extends the network’s lifetime.     

An Integrated Framework for the Design and Optimization of SOC Test Solutions

We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.     

Synthesis of control circuits in folded pipelined DSP architectures

A systematic folding transformation technique to fold any arbitrary signal processing algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set and specified technology constraints, is presented. The folding set specifies the processor and the time partition at which the task is executed and is typically obtained by performing scheduling and resource allocation for the algorithm data-flow graph and the specified iteration period. The constraints imposed on the hardware architecture are also assumed to be known. The technique is used to derive the control circuitry of the hardware architecture. The authors derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators. They propose automatic retiming and pipelining of algorithms described by data-flow graphs for folding. The folding algorithm is applied after preprocessing the data-flow graph for automated pipelining and retiming     

面向电网业务质量保障的5G高可靠低时延通信资源调度方法

该文研究面向电网业务质量保障的5G 高可靠低时延通信(URLLC)的资源调度机制,以高效利用低频段蜂窝通信系统内有限的频谱和功率资源来兼顾电力终端传输速率和调度时延、调度公平性,保障不同电力业务的通信质量（QoS）。首先,基于URLLC的高可靠低时延传输特性,建立电力终端多小区下行传输模型。然后,提出面向系统下行吞吐量最大化的资源分配问题模型并对其进行分步求解,分别提出基于定价机制与非合作博弈的功率分配算法和基于调度时延要求的改进比例公平算法（DPF）动态调度信道资源。仿真结果表明,提出的资源调度方法能在保证一定传输可靠性和公平性的条件下降低电力终端调度时延,满足不同业务等级的QoS需求,与已知算法对比有一定的优越性。     

Jointly optimal routing and scheduling in packet ratio networks

A multihop packet radio network is considered with a single traffic class and given end-to-end transmission requirements. A transmission schedule specifies at each time instant the set of links which are allowed to transmit. The purpose of a schedule is to prevent interference among transmissions from neighboring links. Given amounts of information are residing initially at a subset of the network nodes and must be delivered to a prespecified set of destination nodes. The transmission schedule that evacuates the network in minimum time is specified. The decomposition of the problem into a pure routing and a pure scheduling problem is crucial for the characterization of the optimal transmission schedule     

Resource constrained scheduling of hierarchically structured designactivity networks

In this paper, a new approach to the problem of scheduling of design activities with precedence and multiple resource constraints is proposed. In addition to the AND type relationship, OR and EXCLUSIVE OR relationships may also exist between design activities. In order to handle these logical relationships, IDEF3 is used for network representation. A large network of design activities can be arranged in different levels of abstraction. A procedure is proposed to transform an IDEF3 model into a set of alternative precedence networks. In the networks selected, the activities that are resource independent are grouped with a partitioning procedure. In order to increase the efficiency of the search for the best schedule, a procedure based on the Christofides et al. (1987) reduction procedure is introduced to determine a lower bound on the completion time of the hierarchically structured design activity network     

一种峰值功耗约束下的SoC蚁群测试调度算法

基于扫描链技术的SoC芯片测试可产生比正常使用模式下更大的功耗,这将会对器件可靠性产生不利影响,故在测试时需要将芯片测试功耗控制在允许峰值功耗之下.文中采用蚁群优化思路设计SoC测试调度算法,用于在峰值功耗和TAM总线最大宽度约束下降低SoC测试时间.实验结果表明,本方法优于先前已发表的相关方法.