二维离散余弦变换及其逆变换的VLSI实现

针对适用于H.263及H.264视频压缩协议的编解码算法,二维离散余弦变换(DCT),及二维反离散余弦变换(IDCT),设计了ASIC高速电路,并完成了电路的FPGA模拟验证.在高速算法设计方面,利用一维变换来实现二维变换,通过对变换矩阵的特殊处理,使得一维变换中只含移位和加法运算;在电路设计方面,采用流水线结构并行处理数据,用寄存器堆实现矩阵的转置.对算法及电路设计的优化和改进,大大减少了完成一个矩阵二维正反变换所需要的周期数,提高了电路的吞吐率和运算速度.ASIC设计采用0.18 μm CMOS工艺,在最坏情况下,综合电路可达到的最高频率为250 MHz;FPGA模拟验证最高频率可达170 MHz.     

140万像素高清数字摄像机电路设计

介绍140万像素、每秒7.5帧高清高速数字摄像机的电路设计方案。该设计主要由SONY的CCD ICX205AK,Analog Devices模拟前端电路AD9923A以及Xilinx的FPGA XC3S1200E,TOKYO的JPEG压缩芯片TE3310RPF和ATMEL的ARM芯片AT91RM9200等组成。模拟前端电路AD9923A实现CCD水平和垂直时序的产生,CCD的放大,CCD信号的模数转换三大功能;CCD ICX205AK输出信号经模拟前端电路AD9923A进行放大和模数变换后,输入到FPGA进行数据格式处理,生成YUV信号输入到压缩芯片进行JPEG压缩,然后由ARM通过网络将压缩数据传送到客户端。实验结果表明,该设计方案每秒可以采集、压缩、传输140万像素图像7.5帧。     

从模式I2C总线接口电路设计及其VLSI实现

提出了一种从模式的I^2C总线接口电路，该接口电路实现了对可变参数ASIC芯片的配置。该电路的设计使得可配置的ASIC芯片中参数配置所需要的芯片管脚大大减少。该方案已通过行为仿真和综合后门级时序仿真，并且用无锡上华0.6μmCMOS工艺实现。     

Analysis and Design of a ΔΣ Modulator for Fractional-N Frequency Synthesis

提出了一种适用于分数分频锁相环频率综合器的全数字噪声整型 ΔΣ调制器电路结构新的设计方法,并将其最终实现. 采用了流水线技术和新的CST算法优化多位输入加法器结构，从而降低了整体的复杂度和功耗. 这种电路结构通过了Matlab的行为级仿真，ASIC全定制实现并流片，该结构也通过VHDL综合实现验证，最后给出的测试结果表明该电路具有良好的性能，可应用于单片千兆赫兹级低功耗CMOS频率综合器中.     

一种用于TCOCXO的数据修调电路

采用VIS 0.15 pm BCD工艺设计了一款应用于温度补偿恒温晶体振荡器(TCOCXO)专用集成电路(ASIC)的数据修调电路.该数据修调电路由逻辑控制电路和一种电可擦可编程只读存储器(EEPROM)构成,主要功能是完成TCOCXO ASIC中温度补偿的控制及实现芯片的多模式工作.与通过模拟函数发生器实现的补偿方式相比,使用该数据修调电路实现的温度补偿方法可以实现更高的补偿精度和更小的芯片面积.通过该电路对TCOCXO ASIC进行调试与配置,搭载该ASIC的晶体振荡器在温度为-40～85℃时频率-温度稳定度可达±5×10-9.TCOCXO ASIC的测试结果表明,这种修调方法在减小芯片面积的同时可以实现更高精度的频率-温度补偿.     

基于EPGA与DSP的H．263硬件电路设计

介绍了以DSP与FPGA为核心的H．263的硬件实现电路，电路功能主要由图像采集、处理、传输、显示等部分组成。在该硬件系统中，主要采用了TI公司的图像处理ASIC、高性能浮点运算数字信号处理器（DSP）tms320c6711,以及Xlinix公司的FPGA。其中，FPGA实现ASIC之间的接口电路，DSP实现图像数据的H．263编解码。     

JPEG2000小波变换仿真

提出一种基于JPEG2000中推荐的提升结构的5/3小波变换硬件实现方案。该方案在加载数据的同时进行边界扩展,无须对运算电路进行逻辑控制,可以复用加法器,提高了资源利用率。该方案在FPGA上仿真通过。     

弱电流测量中的电流-频率变换电路

介绍了一种弱电流测量中的电流一频率(I—F)变换电路，它将输入的电流信号直接变换为脉冲频率输出，然后送入计数器计数和计算机处理。并且对其电路原理作了详细的阐述。经过在现场检验和使用，该电路具有工作稳定可靠，灵敏度高，抗干扰能力强等特点。     

智能仪器参数模拟式输入解决方案

分析了ｖ－ｆ变换电路的工作原理，介绍了在智能仪器中，用小型直流电机及ｖ－ｆ变换电路实现参数模拟式输入的方法并给出了实例。     

差分放大电路单端输入信号的射极耦合传输及等效变换

用电路分析的方法对差分放大电路单端输入信号的射极耦合传输及等效变换进行了深入研究,目的是探索单端输入差分放大电路中输入信号的作用过程。差分放大电路的单端输入信号,经差分管的发射极耦合传输,在输入回路可等效变换为差模输入信号、共模输入信号的叠加,且等效变换时与发射极电阻Re取值大小无关,Re取值大小反映了对共模输入信号的抑制程度。所述方法的创新点是给出了单端输入信号在输入回路作用下的物理过程,完善了单端输入信号的等效变换方法。     

一种低功耗2D DCT/IDCT处理器设计

设计了一种低功耗的2D DCT/IDCT处理器。为了降低功耗,设计基于行列分解的结构,采用了Loeffler的DCT/IDCT快速算法,并使用了零输入旁路、门控时钟、截断处理等技术,在满足设计需求的基础上降低了系统的功耗。常系数乘法器是该处理器的一个重要部件,文中基于并行乘法器结构设计了一种新型的低功耗常系数乘法器,它采用了CSD编码、Wallace Tree乘法算法,结合采用了截断处理、变数校正的优化技术,使得2D DCT/IDCT处理器整体性能有较大提高。设计的时钟频率为100 MHz,可以满足MPEG2 MP@HL实时解码的应用。采用SMIC0.18μm工艺进行综合,该2D DCT/IDCT处理器的面积为341 212μm2,功耗为14.971 mW。通过与其他结构的2DDCT/IDCT处理器设计分析与比较,在满足MPEG2 MP@HL实时解码应用的同时,实现了较低的功耗。     

Low-power data-dependent 8/spl times/8 DCT/IDCT for video compression

Traditional fast discrete cosine transform (DCT)/inverse DCT (IDCT) algorithms have focused on reducing arithmetic complexity and have fixed run-time complexities regardless of the input. Recently, data-dependent signal processing has been applied to the DCT/IDCT. These algorithms have variable run-time complexities. A two-dimensional 8/spl times/8 low-power DCT/IDCT design is implemented using VHDL by applying the data-dependent signal processing concept onto the traditional fixed-complexity fast DCT/IDCT algorithm. To reduce power, the design is based on Loeffler's fast algorithm, which uses a low number of multiplications. On top of that, zero bypassing, data segmentation, input truncation and hardwired canonical sign-digit (CSD) multipliers are used to reduce the run-time computation, hence reducing the switching activities and the power. When synthesised using CMC 0.18 /spl mu/m 1.6 V CMOSP technology, the proposed FDCT/IDCT design consumes 8.94/9.54 mW, respectively, with a clock frequency of 40 MHz and a processing rate of 320 Msample/s. This design features lower dynamic power consumption per sample, i.e. it is more power-efficient than other previously reported high-performance FDCT/IDCT designs.     

Condensed recursive structures for computing multidimensional DCT/IDCT with arbitrary length

In this paper, efficient recursive structures for computing arbitrary length M-dimensional (M-D) discrete cosine transform (DCT) and its inverse DCT (IDCT) are proposed. The M-D DCT and IDCT are first converted into condensed one-dimensional (1-D) DCT and discrete sine transform (DST) with a regular preprocessing procedure. The recursive filters for condensed 1-D DCT/DST are then derived by using Chebyshev polynomials to compute M-D DCT/IDCT without data transposition. The proposed structures require fewer recursive loops than traditional 1-D recursive structures, which are realized in M passes and (M-1) data transposition by the so-called row-column approach. With advantages of fewer recursive loops and no transposition memory, the proposed structures attain more accurate results and less power consumption than traditional row-column structures. The proposed recursive M-D DCT/IDCT structures are suitable for very large-scale integration implementation due to regular and modular features.     

Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST

In this paper, new recursive structures for computing radix-r two-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse DCT (IDCT) are proposed. The 2-D DCT/IDCT are first decomposed into cosine-cosine and sine-sine transforms. Based on indexes of transform bases, the regular pre-addition preprocess is established and the recursive structures for 2-D DCT/IDCT, which can be realized in a second-order infinite-impulse response (IIR) filter, are derived without involving any transposition procedure. For computation of 2-D DCT/IDCT, the recursive loops of the proposed structures are less than that of one-dimensional DCT/IDCT recursive structures, which require data transposition to achieve the so-called row-column approach. With advantages of fewer recursive loops and no transposition, the proposed recursive structures achieve more accurate results and less power consumption than the existed methods. The regular and modular properties are suitable for very large-scale integration (VLSI) implementation. By using similar procedures, the recursive structures for 2-D DST and 2-D IDST are also proposed.     

A new algorithm to compute the DCT and its inverse

A novel algorithm to convert the discrete cosine transform (DCT) to skew-circular convolutions is presented. The motivation for developing such an algorithm is the fact that VLSI implementation of distributed arithmetic is very efficient for computing convolutions. It is also shown that the inverse DCT (IDCT) can be computed using the same building blocks which are used for computing the DCT. A DCT/IDCT processor can be designed to compute either the DCT or the IDCT depending on a 1-b control signal     

Design and implementation of a novel linear-array DCT/IDCTprocessor with complexity of order log2N

A new linear-array architecture for computation of both the discrete cosine transform (DCT) and the inverse DCT (IDCT) is derived from the heterogeneous dependence graphs representing the factorised coefficient matrices in the matrix formulation of the recursive algorithm. Using the Kronecker product representation of the order-recursive algorithm, it is observed that the kernel operations of the DCT and IDCT can be merged together by proper input/output data reordering. The processor containing only O(log₂N) stages is fully pipelineable and easily scaleable to compute longer DCT/IDCTs with transform length N to the power of two. Owing to the systematic matrix formulation and the corresponding efficient architectural design, the new DCT/IDCT processor has the advantages of high-throughput rate and low hardware cost. Furthermore, the power consumption can be reduced significantly by turning off the operation of the arithmetic units whenever possible     

A low-power IDCT macrocell for MPEG-2 MP@ML exploiting datadistribution properties for minimal activity

A chip has been designed and tested to demonstrate the feasibility of an ultra-low-power, two-dimensional inverse discrete cosine transform (IDCT) computation unit in a standard 3.3-V process. A data-driven computation algorithm that exploits the relative occurrence of zero-valued DCT coefficients coupled with clock gating has been used to minimize switched capacitance. In addition, circuit and architectural techniques such as deep pipelining have been used to lower the voltage and reduce the energy dissipation per sample. A Verilog-based power tool has been developed and used for architectural exploration and power estimation. The chip has a measured power dissipation of 4.65 mW at 1.3 V and 14 MHz, which meets the sample rate requirements for MPEG-2 MP@ML. The power dissipation improves significantly at lower bit rates (coarser quantization), which makes this implementation ideal for emerging quality-on-demand protocols that trade off energy efficiency and video quality     

H.264中DCT/IDCT/Hadamard变换多时钟方式的FPGA实现

DCT/IDCT/Hadamard变换被广泛应用于多种视频编码标准中,而H.264/MPEG-4AVC作为新一代的视频压缩标准,它具有在相同图像质量下比其他视频压缩标准拥有更高的压缩率的特性[1],因此对于H.264/MPEG-4AVC中的DCT/IDCT/Hadamard变换的研究就有着十分重要的意义。对于H.264/MPEG-4AVC中变换算法进行分析,并且提出一种可用的高效的硬件实现电路结构,此电路结构能够并行计算4输入像素数据。     

基于FPGA和2位串行分布式算法的实时高速二维DCT/IDCT处理器研制

本文在W.Li(1991)循环斜卷积算法和分布式算法的基础上,通过软件模拟和具体硬件设计,利用FPGA完成了可用于高清晰度电视核心解码器及其它信号与信息处理系统的88二维DCT/IDCT处理器的全部电路设计工作。它采用一根信号线控制计算DCT/IDCT,其输入、输出为12位,内部数据线及内部参数均为16位。     

A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI

This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 m triple-layer metal CMOS cell-base technology at 54 MHz.