融合前沿研究的液体电介质击穿教学研究

针对《高电压与绝缘技术》课程中液体电介质的教学难点，提出了融合前沿研究的液体电介质击穿教学方法。基于前沿的液体放电应用背景与先进的液体放电研究平台，形象地展示液体电介质的动态击穿过程，在教学内容、教学方法、考核方式等方面进行科教融合改进，实施“以学生为中心”理念的课程教学设计。该教学方式取得了较好的教学效果，能够为其它知识点的教学质量提升提供参考。     

绝缘系统介质强度的试验电压

家用电子产品防电击的重要性是人所共知的,防电击的主要手段是靠绝缘系统的正确设计及其材料的选择,特别是关键绝缘件的正确设计及选择,并采用合理、正确的方法进行检验。如何在保证人身安全的同时,并兼顾到经济性,一直是生产设计及检测中要考虑的问题。国内外一直在讨论中。张斌同志于一九八六年曾在“电视技术”中简要地介绍过“家用电     

GB8898抗电强度试验电压的分析和选择

分析GB8898抗电强度试验电压在音视频产品中的具体应用，说明如何根据标准曲线确定试验电压的数值，以及参照GB4706．1试验电压的特点来选择电子产品抗电强度试验电压的最佳应用值，供实验室检测人员参考。     

电气强度试验结果辨析

分析电气强度测试的原理和目的,指出电气强度测试作为一种加速测试方法,片面调整相关测试参数是不符合测试目的的.同时,比较电气强度测试的判定方法在型式试验和常规检测中不同的原因,指出正确判定电气强度测试中绝缘材料击穿的方法,重点是围绕绝缘材料被击穿后呈现出导体特性的特点,考察相关电参数的变化特征,以此判定绝缘材料是否被击穿.     

电解质对液体钽电容器闪火电压影响的研究

研究了电解质对高压液体钽电容器电性能的影响。通过对液体钽电容 阳极界面处和阴极界面处的电极过程的研究，结合实验发现，阴离子电子发射及电致伸缩作用引起的Ta2O5介质膜强度下降是导致闪火发生的根本原因。该文研究了电解质中的负离子浓度及有机物的含量对液体钽电解电容器闪火电压的影响。     

耐压强度试验中漏电流的测试方法

通过对耐压强度试验在设备出厂前检验的必要性进行分析,论述了该检测的测试原理及方法,介绍了测试过程中耐压测试仪漏电流的设定限值,保证了电子设备的安全性。     

电流阀值对断续骚扰检测结果的影响

对于某些由开关操作数得出喀呖声率的被测设备,目前大部分检测实验室的断续骚扰分析仪可能会漏计算一些开关操作。解释了标准中"开关操作"的定义,通过实际案例阐述了使用分析仪进行断续骚扰项目检测时,预置电流阀值的选择对检测结果的影响。     

N管开启电压调整注入对P－N结击穿电压的影响

为了讨论问题方便，定义了两种Ｐ－Ｎ结：“漏Ｐ－Ｎ结”和“单纯Ｐ－Ｎ结”。分析了二者击穿电压相关因素的差别，认为“漏Ｐ－Ｎ结”的击穿电压与沟道区杂质浓度密切相关。ＥＥＰＲＯＭ的研制中，要求“漏Ｐ－Ｎ结”击穿电压≥２０Ｖ，即沟道区杂质浓度要低到一定的程度，而同时又必须保证一定的开启电压，即沟道区杂质浓度要高到一定的程度。通过分析与实验，提出了解决这一矛盾的通用原则。     

双电层电容器电解质研究进展

双电层电容器(EDLC)的电解质对电容器的工作电压、内阻、功率特性和温度特性等具有十分重要的影响。EDLC电解质可以分为液体电解质和固体电解质。简介了EDLC电解质的特点和要求。分析了各种电解质的性能、研究了现状和发展趋势。今后很长一段时间内,EDLC电解质的发展方向是宽电位窗口、高电导率、宽使用温度范围和固体化。     

Reinforcing the Built‐In Field for Efficient Charge Collection in Polymer Solar Cells

The collection efficiency of photogenerated charges in polymer solar cells (PSCs) is strongly influenced by the built‐in field (E_in) that develops across the photoactive materials. Here, by investigating the E_in‐development regimes in PSCs by introducing two types of interlayers, electric dipole layers (EDLs) and charge transport layers (CTLs), the device architecture is optimized to result in a larger E_in. By incorporating a pair of EDLs on both sides of the photoactive layer, the E_in is modulated by shifting the vacuum energy at each metal–semiconductor interface, providing a larger E_in than that in conventional PSCs using typical CTLs, such as metal oxides and/or conducting polymers. These devices using paired EDLs exhibit an average PCE of 9.8%, which far surpasses the average PCE of ≈8.5% for paired CTLs.     

Constraint Based Criteria: An Approach for Test Case Selection in the Structural Testing

The selection of test cases to satisfy a structural testing criterion is a very important task because it concerns the quality of the generated test cases. The question is “How to select a test case or path to cover an element required by a structural criterion?” The Constraint Based Criteria are proposed with the goal of answering this question and improving the efficacy, that is, the number of revealed faults. These criteria permit the use of different testing strategies by associating constraints to the required elements. The constraints describe faults generally not revealed by the structural technique. The Constraint Based Criteria can also be used to assess test data sets adequacy.     

A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices

A novel analytical model of the vertical breakdown voltage (V_{B , V} ) on impurity concentration (N_d ) in top silicon layer for silicon on insulator high voltage devices is first presented in this article. Based on an effective ionisation rate considering the multiplication of threshold energy ε_T in the electron, a new formula of silicon critical electric field E_{S , C} on N_d is derived by solving a 2D Poisson equation, which increases with the increase in N_d especially at higher impurity concentration, and reaches up to 68.8?V/µm with N_d  = 1 × 10¹⁷?cm^?3 and 157.2?V/µm with N_d  = 1 × 10¹⁸?cm^?3 from the conventional about 30?V/µm, respectively. A new physical concept of critical energy ε_B is introduced to explain the mechanism of variable high E_{S , C} with heavy impurity concentration. From the E_{S , C} , the expression of V_{B , V} is obtained, which is improved with the increasing N_d due to the enhanced E_{S , C}. V_{B , V} with a dielectric buried layer thickness (t_I ) of 2?µm increases from 428?V of 1 × 10¹⁷?cm^?3 to 951?V of 1 × 10¹⁸?cm^?3. The dependence of N_d and top silicon layer thickness (t_S ) for an optimised device is discussed. 2D simulations and some experimental results are in good agreement with the analytical results.