Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.     

基于高迁移率微晶硅的薄膜晶体管

近年来,微晶硅(μc-Si:H)被认为是一种制作 TFT 的有前景的材料.采用PECVD法,在低于200℃时制作了微晶硅TFTs,其制作条件类似于非晶态 TFTs.微晶硅 TFTs 器件的迁移率超过了 30 cm2/Vs,而阈值电压是 2.5 V.在长沟道器件(50～200 μm)中观测到了这种高迁移率.但对于短沟道器件(2 μm),迁移率就降低到了7 cm2/Vs.此外,该 TFTs 的阈值电压随着沟道长度的减少而增大.文章采用了一种简单模型解释了迁移率、阈值电压随着沟道长度的缩短而分别减少、增加的原因在于源漏接触电阻的影响.     

Improving Switching Performance of Thin-Film Transistors in Disordered Silicon

The silicon integrated electronics on glass or plastic substrates attracts wide interests. The design, however, depends critically on the switching performance of transistors, which is limited by the quality of silicon films due to the materials and substrate process constraints. Here, the ultrathin channel device structure is proposed to address this problem. In a previous work, the ultrathin channel transistor was demonstrated as an excellent candidate for ultralow power memory design. In this letter, theoretical analysis shows that, for an ultrathin channel transistor, as the channel becomes thinner, stronger quantum confinement can induce a marked reduction of OFF-state leakage current (I_OFF), and the subthreshold swing (S) is also decreased due to stronger control of channel from the gate. Experimental results based on the fabricated nanocrystalline silicon thin-film transistors prove the theoretical analysis. For the 2.0-nm-thick channel devices, I_ON/I_OFF ratio of more than 10¹¹ can be achieved, which can never be obtained for normal thick channel transistors in disordered silicon.     

Study of the Drain Leakage Current in Bottom-Gated Nanocrystalline Silicon Thin-Film Transistors by Conduction and Low-Frequency Noise Measurements

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 10¹² cm ^-2 in the upper part of the nc-Si film is reduced to 2.1 times 10¹² cm^-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen     

Amorphous Silicon Thin-Film Transistors Gated Through an Electrolyte Solution

Amorphous silicon thin-film transistors were fabricated on glass substrates in a top-gate configuration in which the metallic gate was replaced by an electrolytic solution with an immersed gate bias electrode. A silicon nitride passivation layer was used to avoid leakage and electrochemical reactions. Transfer and output curves showed transistor behavior. The threshold voltage of ion-sensitive thin-film transistors is controlled by the distribution of charges in solution and molecular dipoles within the $sim!!hbox{1}$ -nm-thick Debye layer at the dielectric–electrolyte interface. The device surface facing the electrolyte was chemically functionalized with a single monolayer of organic molecules, and a gate voltage shift of the order of 100 mV was measured in phosphate buffer upon surface modification.      

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler–Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel–Poole emission.      

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced     

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.      

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design     

Modeling and Parameter Extraction for the Series Resistance in Thin-Film Transistors

A new parameter extraction method is proposed for the series resistance of thin-film transistors (TFTs). By analyzing the gate–source overlap region of staggered structure TFTs, the model for the series resistance is derived and utilized for the parameter extraction. To verify the extraction method, the characteristics of amorphous silicon TFTs obtained from TCAD simulation are used. For the devices with different overlap lengths, the extracted parameters are identical to each other, although the series resistances are different due to the narrow overlap length. When the actual channel length is different from the mask-specified length, the offset length can be effectively corrected by the new method, so that accurate parameters can be obtained. Because the new method has several advantages such as the accuracy and generality over the conventional method, it can be used for further analysis of TFT characteristics.      

Analysis of Negative Bias Temperature Instability in Body-Tied Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.     

Advanced Amorphous Silicon Thin-Film Transistors for AM-OLEDs: Electrical Performance and Stability

We fabricated and characterized the advanced amorphous silicon thin-film transistors with a bilayer structure for both the active and gate dielectric films. The electrical field across the gate insulator has a significant influence on the device threshold voltage electrical stability. We show that high thin-film transistor stability can be achieved even under the presence of a high channel current. Its electrical and high-temperature stability improves up to a factor of five when the TFT biasing condition changes from the linear to the saturation region of operation.     

Microwave ZnO Thin-Film Transistors

We have developed ZnO thin-film transistor design and fabrication techniques to demonstrate microwave frequency operation with 2-$muhbox{m}$ gate length devices produced on GaAs substrates. Using $hbox{SiO}_{2}$ gate insulator and pulsed laser deposited ZnO active layers, a drain–current on/off ratio of $hbox{10}^{12}$, a drain–current density of 400 mA/mm, a field-effect mobility of $hbox{110} hbox{cm}^{2}!/ hbox{V}!cdothbox{s}$, and a subthreshold gate voltage swing of 109 mV/dec were achieved. Devices with Ti-gate metal had current and power gain cutoff frequencies of 500 and 400 MHz, respectively.      

Low-Temperature Pulsed-PECVD ZnO Thin-Film Transistors

We report high-quality ZnO thin films deposited at low temperature (200°C) by pulsed plasma-enhanced chemical vapor deposition (pulsed PECVD). Process byproducts are purged by weak oxidants N₂O or CO₂ to minimize parasitic CVD deposition, resulting in high-refractive-index thin films. Pulsed-PECVD-deposited ZnO thin-film transistors were fabricated on plasma-enhanced atomic layer deposition (PEALD) Al₂O₃ dielectric and have a field-effect mobility of 15 cm²/V s, subthreshold slope of 370 mV/dec, threshold voltage of 6.6 V, and current on/off ratio of 10⁸. Thin-film transistors (TFTs) on thermal SiO₂ dielectric have a field-effect mobility of 7.5 cm²/V s and threshold voltage of 14 V. For these devices, performance may be limited by the interface between the ZnO and the dielectric.     

Approaching Trap-Minimized Polymer Thin-Film Transistors

Semiconducting π-conjugated polymers are the most promising candidates for flexible electronics owing to their facile processability and mechanical robustness; however, achieving steep and stable switching operations in polymer thin-film transistors (TFTs) remains a serious challenge. Herein, it is shown that whole optimizations for eliminating interfacial carrier traps throughout the conductive path are necessary in achieving TFTs showing both exceptionally sharp switching and bias-stress-free characteristics. Inverted-coplanar-type TFTs composed of a highly lyophobic amorphous perfluoropolymer gate–dielectric interfaced with a push-coated semiconducting polymer layer are manufactured. The use of the dielectric allows the establishment of bias-stress-free characteristics with minimized contact resistance. Additionally, fairly sharp on/off switching TFTs with the smallest normalized subthreshold swing can be obtained by utilizing a particular donor–acceptor copolymer that involves a self-passivation mechanism working to achieve a trap-minimized interface. These findings have opened a way for low-power and robust device operations in polymer-based flexible electronics.     

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal–oxide–semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.      

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Using a fluorinated high-k/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-k deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated Ta_infinC_y/HfZrO_infin/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.     

Performances of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors With Trenched Body

Polycrystalline silicon thin-film transistors (TFTs) can be improved by integrating DRAM on chip. However, the TFT's poor capacitance means that traditional DRAMs are infeasible, because they require a capacitor. An alternative, the one-transistor DRAM (1T-DRAM), is promising because it avoids the capacitor by instead storing the logical value as holes trapped in the body region. This letter proposes the use of a trenched body in a TFT to construct a 1T-DRAM. Previously, we have shown that a trenched body reduces the leakage current of a TFT. In this letter, we now show that the trenched-body TFT also works well as a 1T-DRAM device. It has a strong back-gating effect and a programming window that is more than twice as large as that of the conventional TFT.      

Self-Aligned Top-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Self-aligned techniques are often used in conventional CMOS and Si-based thin-film transistors (TFTs) technologies due to various merits. In this paper, we report self-aligned coplanar top-gate InGaZnO TFTs using PECVD a-SiN$_{x}$:H patterned to have low hydrogen content in the channel region and high hydrogen content in the source/drain region. After annealing to induce hydrogen diffusion from a-SiN$_{x}$:H into the oxide semiconductor, the source–drain regions become more conductive and yet the channel region remains suitable for TFT operation, yielding a working self-aligned TFT structure. Such fabrication involves neither back-side exposure nor ion implantation, and thus may be compatible with the typical and cost-effective TFT manufacturing.