适于器件及电路分析的全耗尽短沟道LDD／LDSSOI MOSFET器件模型

本文系统描述了全耗尽短沟道ＬＤＤ／ＬＤＳＳＯＩＭＯＳＦＥＴ器件模型的电压电压特性。该模型扩展了我们原有的薄膜全耗尽ＳＯＩＭＯＳＦＥＴ模型，文中着重分析了器件进入饱和区后出现的沟道长度调制效应，及由于ＬＤＤ／ＬＤＳ区的存在对本征ＭＯＳ器件电流特性的影响。     

AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's

The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO2) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.     

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.     

短沟道SOI MOSFET总剂量辐照效应模型

报道了一个含总剂量辐照效应的 SOI MOSFET统一模型 .该模型能自动计入体耗尽条件 ,不需要分类考虑不同膜厚时的情况 .模型计算结果与实验吻合较好 .该模型物理意义明确 ,参数提取方便 ,适合于抗辐照 SOI器件与电路的模拟 .     

SPICE model and parameters for fully-depleted SOI MOSFET'sincluding self-heating

A simple methodology to accurately extract constant temperature model parameters from static measurements of fully-depleted SOI MOSFET current-voltage characteristics is demonstrated. Self-heating is included in an existing physically-based, short-channel bulk MOSFET model, PCIM, by allowing the temperature to change linearly with power dissipation at each bias point. Only a simple modification of the channel bulk charge in PCIM is necessary to adapt it for SOI. The temperature dependence of the physical parameters (mobility, flatband voltage, and saturation velocity) are also fitted and included in the model. Excellent fit to experimental fully-depleted SOI data is shown over a large range of bias conditions and channel lengths. Once the static SOI data is fitted, the constant temperature model parameters appropriate for circuit simulation are easily extracted     

AC floating body effects and the resultant analog circuit issues insubmicron floating body and body-grounded SOI MOSFET's

We report the extensive study on ac floating body effects of different SOI MOSFET technologies. Besides the severe kink and resultant noise overshoot and degraded-distortion in partially depleted (PD) floating body SOI MOSFET's, we have investigated the residue ac floating body effects in fully depleted (FD) floating body SOI MOSFET's, and the different body contacts on PD SOI technologies. It is important to note that there is a universal correlation between ac kink effect and Lorentzian-like noise overshoot regardless of whether the body is floating or grounded. In addition, it was found that third-order harmonic distortion is very sensitive to floating body induced kink or deviation on output conductance due to the finite voltage drop of body resistance. These results provide device design guidelines for SOI MOSFET technologies to achieve comparable low-frequency noise and linearity with Bulk MOSFET's     

A physical model of floating body thin film silicon-on-insulatornMOSFET with parasitic bipolar transistor

An analytical model for SOI nMOSFET with a floating body is developed to describe the I_ds-V_ds characteristics. Considering all current components in MOSFET as well as parasitic BJT, this study evaluates body potential, investigates the correlations among many device parameters, and characterizes the various phenomena in floating body: threshold voltage reduction, kink effect, output conductance increment, and breakdown voltage reduction. This study also provides a good physical insight on the role of the parasitic current components in the overall device operation. Our model explains the dependence of the channel length on the I_ds-V_ds characteristics with parasitic BJT current gain. Results obtained from this model are in good agreement with the experimental I_ds-V _ds curves for various bias and geometry conditions     

用于器件描述和电路仿真的新型多晶硅TFT直流模型

提出一种新型的多晶硅薄膜晶体管电流-电压物理模型，考虑了陷阱态密度的V形指数分布,运用Lambert W函数推出了表面势的显式求解方法,大大提高了运算效率,在电路仿真中发挥了重要作用，基于指数的陷阱态密度和计算的表面势,描述了亚阈值区和强反型区的漏电流特性。推导了完整、统一的漏电流表达式,包括翘曲效应，在很广的沟道长度范围和工作区内,模型和实验数据一致。     

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 μm have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

用于器件描述和电路仿真的新型多晶硅TFT直流模型

提出一种新型的多晶硅薄膜晶体管电流-电压物理模型.考虑了陷阱态密度的V形指数分布,运用Lambert W函数推出了表面势的显式求解方法,大大提高了运算效率,在电路仿真中发挥了重要作用.基于指数的陷阱态密度和计算的表面势,描述了亚阈值区和强反型区的漏电流特性.推导了完整、统一的漏电流表达式,包括翘曲效应.在很广的沟道长度范围和工作区内,模型和实验数据一致.     

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.     

SOI LDD MOSFET的栅电流的模拟

本文介绍一种采用载流子总量方法分析ＳＯＩ ＭＯＳＦＥＴ器件特性及热载流子效应的数值模型。使用专用模拟程序ＬＡＤＥＳ７联解器件内部二维泊松方程、电子和空穴的连续性方案。ＬＡＤＥＳ７可用于设计和预测不同工艺条件、几何结构对器件性能的影响。该模型直接将端点电流、端点电压与内部载流子的输运过程联系在一起，可准确地模拟ＳＯＩ ＭＯＳＦＥＴ器件的特性并给出清晰的内部物理图象。本文给出了ＬＡＤＥＳ７软件模拟的部     

New aspects and mechanism of kink effect in static back-gatetransconductance characteristics in fully-depleted SOI MOSFETs onhigh-dose SIMOX wafers

An extraordinary kink phenomenon in static back-gate transconductance characteristics of fully-depleted SOI MOSFETs has been experimentally investigated and characterized for the first time. This kink phenomenon has been observed in both NMOS and PMOS on high-dose SIMOX wafers under steady-state conditions at room temperature. It was also found that the back-gate characteristics for both NMOS and PMOS show anomalous shift phenomenon in drain current-back gate voltage (I _D-V_G2) curve at the back-gate voltage corresponding to the kink phenomenon. This kink phenomenon has been attributed to the presence of energetically-localized trap states at SOI/BOX interface. In order to clarify the energy level of the trap states at SOI/BOX interface corresponding to the kink, we have developed a new formula of surface potential in thin-film SOI MOS devices, in which the potential drop across semiconductor-substrate is taken into account. By using this new formula, me have demonstrated that high-dose SIMOX wafers have donor-like electron trap states at ~0.33 eV above the Si midgap with the density of ~N6.0~10¹² cm^-2 eV ^-1 and donor-like hole trap states at ~0.35 eV below the Si midgap with density of ~1.5×10¹² cm^-2 eV^-1 at SOI/BOX interface     

Experimental comparison of RF power LDMOSFETs on thin-film SOI andbulk silicon

Simultaneously fabricated RF power LDMOSFETs on thin-film SOI and bulk silicon wafers. This work compares their DC current-voltage (I-V), capacitance-voltage (C-V), S-parameter, and 1.9-GHz load-pull characteristics and explains differences between them. The SOI LDMOSFET performance is shown to be largely similar to the performance of an equivalent bulk silicon LDMOSFET, but there are important differences. The SOI LDMOSFET has moderately lower on-state breakdown voltage due to increased body resistance. It also has significantly improved power-added efficiency due to reduced parasitic pad losses     

薄膜SOI器件研究与展望

本文详细地分析了薄膜SOI器件一系列有益的特性,如:较大的亚阈值陡度,扭曲(kink)效应的消除以及短沟道效应的削弱等。最后指出,薄膜SOI器件技术是今后设计制造新型亚微米器件及电路的一种有效的方法。     

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs