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1.
Charalampos Kapnistis Konstantinos Misiakos Nikos Haralabidis 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):39-49
A charge sensitive readout chain has been designed and fabricated in acommercially available 0.8 m CMOS technology. The readout chain is optimizedfor pixel detectors measuring soft X-ray energies up to 20 KeV. In the first modean analog signal proportional to input charge is generated and processed in realtime. In the second mode a peak-and-hold operation is enabled and therelevant signal is processed in later time. This dual mode of operation iscontrolled by an external digital signal. The readout chain consists of a chargeamplifier, a shaper, an operational amplifier which can either operate as avoltage amplifier or a peak detector and an output buffer. Its area is
. The gain at the shaper output is 378 mv/fC, theENC is 16
rms at 160 nsec shaping time. The overall gainis 557 mV/fC, the ENC is
rms with 240 nsec peaking timeand 1.4 sec recovery time. The overall power dissipation is 1.5 mWatt with aload capacitance of 25 pF. 相似文献
2.
A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its
value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of
; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At
, the measured
is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications. 相似文献
3.
In pacemaker design the mainconcerns are reliability, functionality,operating life and miniaturization. Afundamental role in miniaturization is dueto the increased circuit integration; hencelow power circuit solutions that can beintegrated in sub-micron CMOS technology arehighly desirable. This work proposes avoltage multiplier suitable for pulse outputgeneration in an implantable pacemaker,implemented in a standard, low-cost CMOS 0.8 m technology. The circuit can operatewithin a supply voltage range of 2.8 V to 2V, corresponding to the voltage capabilityprovided by the single lithium iodine cell,ubiquitously used in pacemaker. Fineprogrammability of the output has beenachieved, thus allowing the choice of theoptimum tradeoff between stimulationefficacy and battery longevity. Moreover theproposed solution takes care of minimizingthe parasitic coupling and disturbancesbetween the charge pump and other blocks inthe system. Finally the measured steady statecurrent consumption is smaller than
. 相似文献
4.
A 5.8 GHz Low Noise Amplifier for Wireless LAN Applications in Silicon Bipolar Technology 总被引:1,自引:0,他引:1
Gerd Schuppener Mehran Mokhtari Boris Kerzar 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):129-136
A monolithic integrated low-noise amplifier for operation in the 5.8-GHzband is described. Two different versions have been implemented where the biasing wasadapted to allow operation over a different range of supply voltage. At 5-V, theamplifiers gain is about 17-dB, with a noise figure of 4.2-dB and 1-dB compressionpoint at –15-dBm input power. The circuits have been designed utilizing a0.6-micron silicon bipolar production technology, featuring npn transistors with
and
of about20-GHz. 相似文献
5.
Arturo Sarmiento-Reyes Octavio González-Castolo 《Analog Integrated Circuits and Signal Processing》2001,28(1):123-129
A fundamental problem of symbolic analysis of electric networks when using the signal-flow (SFG) graph method is to find the common tree of the current and voltage graph (
and
, respectively). In this paper we introduce a novel method in order to determine a common tree of both graphs, which may be used to obtain the symbolic network transfer function when carrying out the small-signal analysis of linear(ised) circuits. 相似文献
6.
A novel figure of merit to describe the bandwidth power efficiency of CMOS transconductors—
is proposed and optimized for cross-coupled differential pair transconductor structures. The optimization is done in two different ways: univariable unconstrained and multivariable constrained. It is revealed that not only dc biases but also ac input phases can affect the bandwidth power efficiency of the transconductor. The bias voltages which can lead to best
ratio at different ac phase combinations are obtained and presented in the article. HSPICE simulations are conducted to verify the theoretical predictions. On the basis of the cross-coupled differential pair transconductor, a biquadratic transconductor-C filter configuration is implemented. The frequency vs. power characteristic of the filter is studied for both optimally- and non-optimally-biased transconductor. It is shown that the
optimization of the transconductor structure can result in performance improvement of the transconductor-C filter. The deviation of the optimal bias condition between the transconductor alone and the transconductor-C filter due to the inclusion of peripheray circuitries in the filter is discussed in the article. 相似文献
7.
In this paper several examples of circuits obtained with an automatic synthesis algorithm will be shown. The algorithm, described in a companion paper [1] and outlined here for clarity, has been implemented in the Mathematica
language. We applied the new algorithm to classical problems of inmittance synthesis, obtaining well known topologies and also non-reported structures. When the algorithm is applied to challenging new problems, novel and practically useful inmittances are synthesized. 相似文献
8.
Maria Alessandra Fasoli 《Multidimensional Systems and Signal Processing》1998,9(3):291-306
Let K be a field, k and n positive integers and let
matrices with coefficients in K. For any function
there exists a unique solution
of the system of difference equations
defined by the matrix-k-tuple
such that
. The system
is called finite-memory system iff for every function g with finite support the values
are 0 for sufficiently big
. In the case
, these systems and the corresponding matrix-k-tuples have been studied in bis, fm, fmv, fv1, fv, fz. In this paper I generalize these results to an arbitrary positive integer k and to an arbitrary field K. 相似文献
9.
This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel array of sample-and-hold amplifiers for analog delay line. The sample-and-hold amplifier includes the open-loop unity-gain amplifier with gain-control circuit using replica-biasing scheme, which also improves uniformity among amplifiers. It was fabricated in a 0.8-m CMOS technology and consumes power of 200 mW for
V power supply voltage. 相似文献
10.
In this paper we investigate -bit serial addition in the context of feed-forward linear threshold gate based networks. We show that twon-bit operands can be added in
overall delay with a feed-forward network constructed with
linear threshold gates and
latches. The maximum weight value is
and the maximum fan-in is
. We also investigate the implications our scheme have to the performance and the cost under small weights and small fan-in requirements. We deduce that if the weight values are to be limited by a constantW, twon-bit operands can be added in
overall delay with a feed-forward network that has the implementation cost [logW]+1, in terms of linear threshold gates,
in terms of latches and a maximum fan-in of 3[logW]+1. We also prove that, if the fan-in values are to be limited by a constantF+1, twon-bit operands can be added in
overall delay with a feed-forward network that has the implementation cost
, in terms of linear threshold gates,
in terms of latches, and a maximum weight value of
. An asymptotic bound of
is derived for the addition overall delay in the case that the weight values have to be linearly bounded, i.e., in the order ofO(n). The implementation cost in this case is in the order ofO(logn), in terms of linear threshold gates, and in the order ofO(log2
n), in terms of latches. The maximum fan-in is in the order ofO(logn). Finally, a partition technique, that substantially reduces the overall cost of the implementation for all the schemes in terms of delay, latches, weights, and fan-in with some few additional threshold gates, is also presented. 相似文献
11.
Tomerlin Andrew T. Edmonson William W. 《Multidimensional Systems and Signal Processing》2002,13(3):333-340
Consider the class of d-dimensional causal filters characterized by a d-variate rational function
analytic on the polydisk
. The BIBO stability of such filters has been the subject of much research over the past two decades. In this paper we analyze the BIBO stability of such functions and prove necessary and sufficient conditions for BIBO stability of a d-dimensional filter. In particular, we prove if a d-variate filter H(z) analytic on
has a Fourier expansion that converges uniformly on the closure of
, then H(z) is BIBO stable. This result proves a long standing conjecture set forth by Bose in [3]. 相似文献
12.
We propose using the TCP decoupling approach to improve a TCP connection's goodput over wireless networks. The performance improvement can be analytically shown to be proportional to
, where MTU is the maximum transmission unit of participating wireless links and HP_Sz is the size of a packet containing only a TCP/IP header. For example, on a WaveLAN [32] wireless network, where MTU is 1500 bytes and HP_Sz is 40 bytes, the achieved goodput improvement is about 350%. We present experimental results demonstrating that TCP decoupling outperforms TCP reno and TCP SACK. These results confirm the analysis of
performance improvement. 相似文献
13.
CMOS Front-end Amplifier Dedicated to Monitor Very Low Amplitude Signal from Implantable Sensors 总被引:2,自引:0,他引:2
We describe in this paper a low-noise, low-power and low-voltage analog front-end amplifier dedicated to very low amplitude signal recording and processing applications. Our main focus is acquiring action potentials from peripheral nerves to recuperate lost functions in paralyzed patients. Low noise and low DC offset are realized using Chopper stabilization (CHS) technique. In addition, due to the use of a rail-to-rail input stage, low power supply (1.8 V) and wide common mode input range (0–1.8 V) are achieved also. It features a gain of 51 dB and a bandwidth of 4.5 kHz. The equivalent input noise is about 56 nV/
. The proposed preamplifier includes a matching clock generator, a 4th order continuous-time low-pass filter and an instrumentation amplifier. The proposed design has been implemented in 0.35 m double-poly n-well CMOS process with an active die area of 450 × 1150 m2. The total data acquisition device consumes only 775 W. 相似文献
14.
Interfacial reactions of Y and Er thin films on both (111)Si and (001)Si have been studied by transmission electron microscopy
(TEM). Epitaxial rare-earth (RE) silicide films were grown on (111)Si. Planar defects, identified to be stacking faults on
planes with 1/6
displacement vectors, were formed as a result of the coalescence of epitaxial silicide islands. Double-domain epitaxy was
found to form in RE silicides on (001)Si samples resulting from a large lattice mismatch along one direction and symmetry
conditions at the silicide/(001)Si interfaces. The orientation relationships are [0001]RESi2−x//
Si,
RESi2−x//(001)Si and [0001]RESi2−x/
Si,
RESi2−x//(001)Si. The density of staking faults in (111) samples and the domain size in (001) samples were found to decrease and
increase with annealing temperature, respectively. 相似文献
15.
The ability of a parallel algorithm to make efficient use of increasing computational resources is known as its scalability. In this paper, we develop four parallel algorithms for the 2-dimensional Discrete Wavelet Transform algorithm (2-D DWT), and derive their scalability properties on Mesh and Hypercube interconnection networks. We consider two versions of the 2-D DWT algorithm, known as the Standard (S) and Non-standard (NS) forms, mapped onto P processors under two data partitioning schemes, namely checkerboard (CP) and stripped (SP) partitioning. The two checkerboard partitioned algorithms
(Non-standard form, NS-CP), and as
(Standard form, S-CP); while on the store-and-forward-routed (SF-routed) Mesh and Hypercube they are scalable as
(NS-CP), and as
(S-CP), respectively, where M
2 is the number of elements in the input matrix, and (0,1) is a parameter relating M to the number of desired octaves J as
. On the CT-routed Hypercube, scalability of the NS-form algorithms shows similar behavior as on the CT-routed Mesh. The Standard form algorithm with stripped partitioning (S-SP) is scalable on the CT-routed Hypercube as M
2 = (P
2), and it is unscalable on the CT-routed Mesh. Although asymptotically the stripped partitioned algorithm S-SP on the CT-routed Hypercube would appear to be inferior to its checkerboard counterpart S-CP, detailed analysis based on the proportionality constants of the isoefficiency function shows that S-SP is actually more efficient than S-CP over a realistic range of machine and problem sizes. A milder form of this result holds on the CT- and SF-routed Mesh, where S-SP would, asymptotically, appear to be altogether unscalable. 相似文献
16.
T. Nishihara M. Shinohara O. Ishiyama F. Ohtani M. Yoshimoto T. Maeda H. Koinuma 《Journal of Electronic Materials》1996,25(5):667-670
The topmost atom of InP (001) surfaces, which were annealed at temperatures between 300 and 550°C or sputtered with 1 keV
Ar+ at 300°C in ultra high vacuum, has been directly identified by means of coaxial impact collision ion scattering spectroscopy
(CAICISS). Time-of-flight spectra of the annealed InP (001) surface exhibited both In and P peaks in both
azimuth and in [100] azimuth, which revealed that the topmost layer of annealed InP (001) was comprised of In-terminated
and P-terminated surfaces. On the other hand, time-of-flight spectrum of the InP (001) sputtered at 300°C revealed only an
In peak in
azimuth and revealed both In and P peaks in [100] azimuth. This result indicates that the topmost layer on the Ar+-sputtered InP (001) surface was completely terminated by In atoms. Furthermore, we indicate that surface damage induced by
this sputtering treatment is little. The azimuthal depen-dence of CAICISS intensity scattered from In and P showed twofold
symmetry with respect to [100] direction, which originated from the zinc-blende structure. 相似文献
17.
The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor
and
values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper. 相似文献
18.
Yuyu Chang John Choma Jr. Jack Wills 《Analog Integrated Circuits and Signal Processing》2001,28(1):43-52
A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two
-enhancement techniques are utilized to circumvent the low
characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of
tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and –20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW. 相似文献
19.
Creep behavior of eutectic Sn-Cu lead-free solder alloy 总被引:3,自引:0,他引:3
Tensile creep behavior of precipitation-strengthened, tin-based eutectic Sn-0.7Cu alloy was investigated at three temperatures
ranging from 303–393 K. The steady-state creep rates cover six orders of magnitude (10−3−10−8 s−1) under the stress range of σ/E=10−4−10−3. The initial microstructure reveals that the intermetallic compound Cu6Sn5 is finely dispersed in the matrix of β-Sn. By incorporating a threshold stress, σ
th, into the analysis, the creep data of eutectic Sn-Cu at all temperatures can be fitted by a single straight line with a slope
of 7 after normalizing the steady-state creep rate and the effective stress, indicating that the creep rates are controlled
by the dislocation-pipe diffusion in the tin matrix. So the steady-state creep rate,
, can be expressed as
exp
, where Qc is the activation energy for creep, G is the temperature-dependent shear modulus, b is the Burgers vector, R is the universal
gas constant, T is the temperature, σ is the applied stress, A is a material-dependent constant, and
, in which σ
OB is the Orowan bowing stress, and kR is the relaxation factor.
An erratum to this article is available at . 相似文献
20.
A DDS Synthesizer with Digital Time Domain Interpolator 总被引:4,自引:0,他引:4
Timo Rahkonen Harri Eksyma Antti Mäntyniemi Heikki Repo 《Analog Integrated Circuits and Signal Processing》2001,27(1-2):111-118
A DDS type circuit structure for producing numericallyprogrammable square wave clock signal is presented. The high speed D/Aconverter needed in conventional DDS systems is replaced by an
tap delay line time domain interpolator thateffectively increases the sampling rate by a factor of
. Thus the circuit can be used up to full clock rate withoutimage filtering. A prototype IC with clock frequency of 30 MHz, 5 bitinterpolator and SFDR of –40 dBc up to 10 MHz and –33 dBcup to 15 MHz has been designed and tested. 相似文献