A New Partial-SOI LDMOSFET With Modified Electric Field for Breakdown Voltage Improvement

For the first time, we report a novel partial-silicon-on-insulator (PSOI) lateral double-diffused MOS field-effect transistor where the buried oxide layer consists of two sections with a step shape in order to increase the breakdown voltage. This new structure is called step buried oxide PSOI (SB-PSOI). We demonstrate that an electric field was modified by producing two additional electric field peaks, which decrease the common peaks near the drain and source junctions in the SB-PSOI structure. Two-dimensional simulations show that the breakdown voltage of SB-PSOI is nearly four to five times higher in comparison to its PSOI counterpart. Moreover, we elucidate operational principles, as well as design guidelines, for this new device.      

ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of It2 between VDMOS and LDMOS transistors

This paper presents the device‐level electrostatic discharge (ESD) robustness improvement for integrated vertical double‐diffused MOS (VDMOS) and lateral double‐diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate‐voltage dependence of the second breakdown current (I_t2) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Investigation of a novel SOI LDMOS using p+ buried islands in the drift region by numerical simulations

A novel SOI LDMOS with p+ buried islands and p-top layer in the drift region (PBI SOI) is proposed in this letter. At off-state, the high potential is induced from the drain region to the inside of the drift region. The p+ buried islands cause reduced surface field effect and modulate the electric field distribution in the drift region. The buried p-top layer withstands the lateral drain voltage. Thus, the breakdown voltage (BV) of PBI SOI is significantly improved. Meanwhile, the specific on-resistance \((R_\mathrm{on,sp})\) is reduced by improving doping concentration of the drift region, owing to the assisting depletion effect caused by the p+ buried islands. Consequently, the \(R_\mathrm{on,sp}\) of the proposed structure is reduced by 53.7% compared with the conventional SOI LDMOS at the same half-pitch size, the BV and the figure-of-merit \((\hbox {FOM} = \hbox {BV}^{2}/ R_\mathrm{on,sp})\) are observably improved by 24.8% and 235.9% respectively.     

Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor

We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact.     

A modified LDMOS device with improved ESD protection performance

A modified lateral‐diffusion metal–oxide–semiconductor (MLDMOS) device with improved electrostatic discharge (ESD) protection performance is proposed for high‐voltage ESD protection. In comparison with the traditional LDMOS and the LDMOS with an embedded silicon‐controlled rectifier (LDMOS‐SCR), the proposed device has better ESD robustness and higher holding voltage. By optimizing key parameters, such as the spacing between the drain and the poly gate, the effective channel length, and the number of fingers, the MLDMOS can achieve a maximum failure current over 80 mA/µm, which is larger than that of LDMOS‐SCR. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

An ultralow‐capacitance bidirectional punch‐through transient voltage suppressor

A bidirectional punch‐through transient voltage suppressor based on a five‐layer N⁺⁺P⁺PP⁺N⁺⁺ structure is developed. By realizing the device using a 12‐finger layout, transmission line pulse measurements indicate that the device has met the IEC61000‐4‐2 standard with electrostatic discharge robustness of ±8 kV and has an ultralow capacitance value of less than 0.17 pF. Under 3.3 V forward or reverse bias, the device exhibits a leakage current of less than 2 nA. These excellent figures suggest that the developed structure is well suited for actual system‐level protection applications. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate

An ultra-low specific on-resistance \((R_\mathrm{{on,sp}})\) trench SOI LDMOS with a floating vertical field plate structure (FVFPT SOI) is proposed in this paper. A floating vertical plate (FVFP) is introduced into the filled oxide trench of a conventional trench SOI LDMOS (CT SOI) to improve its electrical performance. We conduct related performance analysis to this device by simulation and investigate the effects of different parameters on its performance. The FVFP causes an assisted depletion effect especially for the trench surface regions. An ultra-low \(R_\mathrm{{on,sp}}\) is therefore obtained in the FVFP device due to higher drift region doping concentration \((N_\mathrm{{d}})\). A breakdown voltage (BV) of 188V and a \(R_\mathrm{{on,sp}}\) of \(0.9 \hbox { m}\Omega \, \hbox { cm}^{2}\) are realized on a 4.8-\({\upmu }\hbox {m}\)-long drift region, a 7.5-\({\upmu }\hbox {m}\)-thick top-silicon layer and a 0.5-\({\upmu }\hbox {m}\)-thick buried oxide (BOX) layer by our simulation. Eventually, the \(R_\mathrm{{on,sp}}\) for the FVFPT SOI can be reduced by more than 60%, while its BV is maintained the same class as the CT SOI, and the figure of merit (FOM) is enhanced by 155%. And a set of optimal parameters, including the structure parameters of plate and the property parameters of device, are obtained.     

Impact of platinum contamination on ferroelectric memories

Abstract

The impact of platinum contamination on the breakdown properties of gate oxide is reported. Wafers were intentionally contaminated with 1×10¹³ to 4×10¹⁴ at/cm² Pt after a 7.5 nm gate oxide growth, 300 nm poly-silicon deposition and subsequent phosphorus doping. Breakdown characteristics were evaluated using a voltage ramp method. The current-voltage curves of MOS capacitors show very few low field breakdown events, and the main field breakdown occurs at 12 MV/cm. If compared to clean wafers, platinum does not increase the defect density seriously. It is found from the E-Ramp results that platinum contamination up to 4×10¹⁴ at/cm² does not have a pronounced effect on the gate oxide integrity if the contamination occurs after front-end-of-line processing of device fabrication.     

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

In this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N⁺ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N⁺ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.     

A high-performance IGBT with new N+ buffer structure

We propose a new IGBT structure with a new N⁺ buffer, and confirm by experiments and numerical simulations that the new IGBT is superior to the conventional one. The following results were obtained. (1) According to our experiments, the new IGBT was able to decrease the total power loss, and the parallel operation became easier, compared with the conventional IGBT. Moreover, the short-circuit ruggedness of the new IGBT was almost the same as that of the conventional one by optimizing the ratio of the N⁺⁺ buried layer. (2) We clarified why the characteristics of the new IGBT were improved by numerical simulations. (a) When the new IGBT is on, holes injected from the P⁺ substrate flow through, remaining out of the N⁺⁺ buried layer. Also, the holes rapidly turn around in the N⁺⁺ buried layer when passing by, and the hole concentration becomes even. Because the lifetime of the new IGBT is designed to be long, the hole concentrations of the new IGBT increases in the N⁻ layer. Therefore, the saturation voltage of the new IGBT is lower than that of the conventional IGBT. (b) Since the lifetime of the N⁻ layer of the new IGBT can be extended, the temperature dependence of the lifetime becomes small, and IZTC of the new IGBT is improved. (c) In the turn-on state, the holes are injected through the N⁺ buffer layer with lower concentration from the P⁺ substrate, thus the turn-on speed of the new IGBT become quicker and the turn-on loss of the IGBT is reduced. (d) In the turn-off state, as the N⁻ layer is depleted completely, the carriers in the N⁺ buffer layer mainly influence the tail current. There are few carriers in the N⁺⁺ buried layer of the new IGBT, so the turn-off loss of the new IGBT is reduced. (e) Since the effect to prevent the holes being injected from the P⁺ substrate affects the N⁻ layer, the number of carriers of the N⁻ layer of the new IGBT is limited in the saturation current region. Therefore, the saturation current is also controlled, and the short-circuit ruggedness of the new IGBT is not diminished. © 1998 Scripta Technica, Electr Eng Jpn, 124(4): 37-46, 1998     

Lateral trench oxide Schottky rectifier on SOI for power integrated circuits

In this paper, a Lateral Trench Oxide Schottky (LTOS) rectifier on silicon-on-insulator suitable for power integrated circuits is presented. The proposed structure utilizes a surface Schottky contact with vertical field-plate placed in a trench filled with oxide. The field-plate reduces the electric field on the Schottky contact and suppresses the barrier lowering effect leading to significant improvement in the device performance. Further, the proposed structure folds the drift region in vertical and horizontal directions resulting substantial reduction in pitch length of the device. Two-dimensional numerical simulations have been performed to analyse and optimize the performance of proposed device and results are compared with that of the conventional lateral Schottky rectifier. The LTOS rectifier provides 60 % improvement in breakdown voltage and 50 % reduction in pitch length as compared to the conventional device while maintaining low forward voltage drop and low reverse leakage current.     

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

This paper discusses the hot-carrier and electrical safe operating area (SOA) of trench-based integrated power devices. The hot-carrier SOA is determined by the avalanche current, exhibiting a maximum at intermediate drain voltage. The initial hot-carrier degradation is dependent on the crystal plane on which the gate oxide is grown. During hot-carrier stress, interface states are formed in the device's accumulation region. No channel degradation is observed. The electrical SOA of the trench-based MOS (TB-MOS) is much larger than a comparable lateral DMOS (LDMOS) or vertical DMOS (VDMOS). Even for 100-ns pulses, the TB-MOS exhibits electrothermal effects, contrary to LDMOS and VDMOS. Finally, the intrinsic gate oxide quality of the trench gate oxide is reported on. It is proven that the oxide time-dependent dielectric breakdown is determined by the thinnest oxide along the trench sidewall.      

A termination structure of 2.5kV IGBT with field plate and semi‐resistive (SIPOS) layer

A junction termination with a field plate combined with a semi‐resistive layer deposited on front oxide layer is proposed for the first time as a termination structure of a 2.5 kV IGBT which allows high forward blocking voltage. The voltage handling capability of the proposed structure is compared with that for the conventional multiful floating ring structure and verified by the two‐dimensional device simulator, MEDICI. The numerically calculated breakdown voltages are 2205 and 2471 V for the multiple floating ring and proposed structures, respectively, yielding 11.3% improvement in the breakdown voltage. The breakdown voltage can be enhanced to 2500 V for the proposed structure when a floating ring is located at the edge of the field plate under the oxide. Copyright © 2003 John Wiley & Sons, Ltd.     

Updated structure of vertical double-diffused MOSFETs for irradiation hardening against single events

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm²/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.     

Performance evaluation of a lateral trench-gate power MOSFET on InGaAs

In this paper, an integrable lateral trench-gate metal-oxide-semiconductor (LTGMOS), a power MOSFET on In_0.53Ga_0.47As is presented. The device consists of two separate trenches built in the drift region in which two gates are placed on both sides of the P-body region. The trench-gate structure not only enhances the drain current due to parallel conduction of two channels but also causes the reduced-surface-field effect in the device resulting significant improvement in the device performance. Two-dimensional numerical simulations have been performed to analyse and compare the performance of the proposed device with that of the conventional lateral MOSFET. The LTGMOS provides 2.3 times higher output current, 29 % decrease in threshold voltage, 42 % reduction in on-resistance, 47 % improvement in peak transconductance, two times higher breakdown voltage, and 5.8 times improvement in the figure-of-merit over the conventional device for the same cell pitch.     

A novel symmetrical 4H–SiC MESFET: an effective way to improve the breakdown voltage

In this paper, a novel symmetrical structure (SS) of 4H–SiC metal semiconductor field effect transistor (MESFET) as an effective way to improve the breakdown voltage is presented. The key idea in this work is to improve the breakdown voltage, maximum output power density, and frequency parameters of the device using a symmetrical structure with recessed gate. The SS-MESFET modifies the electric field in the drift layer significantly. The influence of the SS-MESFET on the saturation current, breakdown voltage \((\hbox {V}_{\mathrm{BR}})\), and small-signal characteristics of the SS-MESFET are studied by numerical device simulation. Using two-dimensional device simulation, we demonstrate that the breakdown voltage \((\hbox {V}_{\mathrm{BR}})\) improved by factors 2.5 and 3.3 in comparison with an asymmetrical conventional MESFET structure (AC-MESFET) and a symmetrical conventional MESFET structure (SC-MESFET), respectively. Also, the maximum output power density \((\hbox {P}_{\mathrm{max}})\) improved about by 93 and 250 % in comparison with the AC-MESFET and SC-MESFET structures, respectively. So, the SS-MESFET shows the superior maximum available gain (MAG), unilateral power gain (U), and current gain \((\hbox {h}_{12})\) which is presenting the proposed structure is more suitable device for high power microwave applications.     

Improved Performance of Stair-Stepping Buffer-Gate 4H Silicon Carbide Metal Semiconductor Field Effect Transistor

Abstract

The 4H SiliconCarbide metal semiconductor field effect transistor (4H-SiC MESFET) with a buffer layer between the gate and channel (BG) is optimized and a new stair-stepping buffer-gate structure (SBG) is proposed for improving the breakdown characteristics. The terminal technology of breakdown point transfer (BPT) is applied in 4H-SiC SBG-MESFET in order to scatter the electric field lines and transfer the breakdown point. The breakdown mechanism is further investigated by simulating the surface electric field distribution and electrostatic potential contours. The results show that the breakdown voltage is increased from 120?V to 180?V, improved by the rate of 50% while the current density has hardly deteriorated, and thus the current density is improved from 9.35?W/mm to 13.2?W/mm in comparison with BG structure.     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

The Fabrication and Experimental Results of a New Lateral Trench Electrode IGBT with a p+ Diverter

A new Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) with a p+ diverter was proposed and fabricated to improve the electrical characteristics of the conventional LTIGBT. The p+ diverter was placed between anode and cathode electrodes. Because the p+ diverter region of the proposed device was enclosed trench oxide layer, the electric field centered trench-oxide layer, and punch through breakdown of LTEIGBT with p+ diverter was occurred at the high breakdown voltage. Therefore, the p+ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. As a results of device simulation, the electrical characteristics of the proposed LTEIGBT including latching current density, breakdown voltage and switching speed was superior to conventional devices. After simulation was finished, we fabricated and analyzed the proposed LTEIGBT with a p+ diverter. The maximum current of the proposed device and conventional device were 90 mA and 70 mA, respectively. Therefore, The proposed LTEIGBT with a p+ diverter is effective device for smart power IC.