Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

An investigation of the contact resistance of a commercial elastomer interconnect under thermal and mechanical stresses

The contact behavior of a commercial elastomer interconnect, composed of silicone rubber and silver particles, was evaluated under thermal and mechanical stresses. Its contact resistance demonstrated a linear relationship in a log-log plot with contact force at room temperature; however, a deviation of the trend occurred when temperature was changed. With the interconnect compressed under a constant force, a fluctuation in contact resistance was initiated by a change of temperature. This phenomenon may be attributed to the inherent conduction mechanisms of the elastomer interconnect. The multiple interfaces between metal particles make the contact sensitive to a variety of factors. This sensitivity may have a direct impact on its long-term reliability.     

海量连接解决方案的优势

海量连接系统是建立在测试仪器和被测单元之间标准化的连接。通过测试仪端的接收器和被测单元上的适配器相连接,海量连接系统可以同时轻松连接各种类型的I/O,这样不但简化了测试过程,还消除了其它类型的连接器连接时所易产生的错误。海量连接系统与使用自定义接口的测试系统相比,具备很多优势:例如模块化、可维护性、易于升级、可扩展。海量连接系统的模块化配置使得大量小信号、电源、射频     

First-principles investigation of Sn doping on the geometric and electronic structures of V2O5

Abstract

The influence of Sn doping on the geometric and electronic structures of V₂O₅ were investigated by the plane-wave pseudopotential technique based on density functional theory (DFT) with LDA/CA-PZ functional. After Sn doping, the unit cell volume of V₂O₅ increases slightly and the system changes from intrinsic semiconductor to n-type semiconductor. In the Sn doped V₂O₅, the V-O bonds show a significant covalent bond character, while the Sn-O bonds exhibits mainly ionic bond character; the V?=?O bonds from the vanadium and terminal oxygen have the strongest bond strength among all the V-O bonds in the system; in addition, the bond strength of the terminal/apical V-O bonds adjacent to Sn atom weakens obviously.     

高速互连中信号完整性测试单元分析

介绍了高速互连中的信号完整性故障,主要探讨了由NMOS和PMOS管组成的内建高速互连检测单元,该单元用于对高速互连中的信号完整性故障进行测试。主要对已提出的2种故障检测单元进行了对比,分析了它们在信号完整性故障测试方面的不同特点,并用Hspice在有无噪声情况下进行了仿真,在理论分析和仿真结果方面显示了良好的一致性。     

基于RLC模型的集成电路互连线串扰估计

本文提出了一个新的基于RLC模型的高速集成电路互连线串扰峰值估计公式,在考虑了电感效应的基础上建立了RLC电路模型,对CMOS电路器件作了线性假设,推导出了当侵略线输入单位斜升信号时的互连串扰时域表达式。计算机仿真结果表明,该公式的结果相对于HSPICE仿真的误差绝对值小于10%,可被应用于集成电路版图综合的布局规划模型中,能够在高速、高密度VLSI的设计阶段预测信号性能。     

Kron-Branin modeling of symmetric star tree interconnect

An analytical modeling method of symmetric tree interconnect is developed in this paper. The tree topology is composed of multibranch distributed interconnects of printed circuit board (PCB). The interconnects are constituted by elementary transmission line (TL) defined by its characteristic impedance and propagation constant. The star symmetric tree model is built with the Kron-Branin (KB) formalism elaborated with the graph topology. Reduction method allowing to simplify the graph from single-input multiple-output (SIMO) to single-input single-output (SISO) circuit is used. The interconnect tree branch currents are determined from the reduced SISO structure. The symmetric tree S-parameter and access and transfer impedance models are expressed in function of constituting elementary TL parameters with the KB formalism. The particular behaviors of short-circuit and open-ended star tree are investigated versus the tree number of output branches. The developed KB model effectiveness is validated with microstrip star tree designed and simulated with a 3D electromagnetic computational and electronic circuit designer commercial tool. Three different proofs of concept (POC) of star trees comprised of three-output, four-output, and five-output branches are computed. The simulated reflection and transmission coefficients from DC to 5 GHz are in good agreement with the KB models. The proposed model is potentially useful for the PCB complex interconnect modeling and signal integrity analysis.     

Numerical simulation of electrical characteristics in nanoscale Si/GaAs MOSFETs

In this paper, electrical characteristics of metal-oxide-semiconductor field effect transistor (MOSFET) with silicon/gallium-arsenic (Si/GaAs) stacked film are numerically studied. By calculating several important device characteristics, such as the on-state current, the subthreshold swing, the drain induced barrier lowering, the threshold voltage, the threshold voltage roll-off, and the output resistance, a 50 nm Si/GaAs MOSFET is simulated with respect to different thicknesses of Si/GaAs film. Compared with the results of pure Si MOSFET, Si/GaAs MOSFET shows promising characteristics after properly selecting the thickness of Si/GaAs film. Among Si, germanium (Ge), and Si/Ge MOSFETs, Si/GaAs MOSFET relatively exhibits a higher driving capability due to higher carrier mobility within the Si/GaAs film. However, quantitatively accurate estimation of device characteristics will depend upon more precise calculation of band structure of the stacked film.     

An investigation of thick PZT films for sensor applications: A case study with different electrode materials

Lead zirconate titanate (PZT) is a piezoelectric material that can sense or respond to mechanical deformations and can be used in ceramic micro-electro-mechanical systems (C-MEMS). A thick-film paste was prepared from a pre-reacted PZT powder (PbZr_0.53Ti_0.47O₃) and thick-film technology (screen-printing and firing) was used to deposit the PZT layers on LTCC tapes and on alumina substrates. The microstructural, electrical and piezoelectric characteristics of the thick PZT films on relatively inert alumina substrates and on LTCC tapes were studied. Preliminary experiments indicated that due to the interaction between the printed PZT layers and the LTCC substrates during firing the electrical characteristics deteriorate significantly. To minimise the influence of substrate-film interactions different electrode materials and the use of additional intermediate layers as a barrier were evaluated. The dielectric permittivities, dielectric losses, and piezoelectric coefficients (d ₃₃) were measured. The dielectric permittivities of the thick films fired on LTCC substrates were lower (210 with gold electrodes and 430 with silver electrodes) than those measured on alumina substrates (500). The piezoelectric coefficients d₃₃ were measured with a Berlincourt piezometer. The d ₃₃ values measured on the LTCC substrates were relatively low (60–80 pC/N) compared with the values obtained for the alumina substrates (around 140 pC/N). The lower dielectric constants and piezoelectric coefficients d ₃₃ of the films on LTCC substrates are attributed to the formation of phases with a lower permittivity. This was a result of the diffusion of SiO₂ from the LTCC into the active PZT layer. The diffusion of silica was confirmed by the SEM and EDS analyses.     

Calibration of MEMS-based test structures for predicting thermomechanical stress in integrated circuit interconnect structures

This paper uses a rotating-beam-sensor structure to show that the extrinsic stress from the mismatch in expansion coefficient between the aluminum and the silicon substrate dominates over the compressive stress from the sputter growth. Sintering the layers at temperatures above 150/spl deg/C reduces this compressive stress due to the action of creep. Calibration of the rotation of the device has been undertaken by direct comparison to high resolution X-ray-diffraction measurements and these show that the sensor has a resolution better than 2.8 MPa. Furthermore, we have used the sensor to investigate the variation of in-plane stress with the compliance of the intermetal dielectric, by directly comparing sensors fabricated on SiO/sub 2/ and polyimide layers.     

Plasmonic tweezers: for nanoscale optical trapping and beyond

Optical tweezers and associated manipulation tools in the far field have had a major impact on scientific and engineering research by offering precise manipulat...     

Gate-stack optimization of a vertically stacked nanosheet FET for digital/analog/RF applications

Journal of Computational Electronics - Nanosheet field effect transistors (NS-FET) are a most promising candidate for next-generation semiconductor devices for sub-7-nm technology nodes. This work...     

An ultra-energy-efficient crosstalk-immune interconnect architecture based on multilayer graphene nanoribbons for deep-nanometer technologies

An ultra-energy-efficient interconnect structure based on multilayer graphene nanoribbon (MLGNR) interconnects for deep-nanometer technologies is proposed herein. First, a low-swing interconnect based on MLGNRs and high-performance interface circuits using carbon nanotube field-effect transistors (CNTFETs) is proposed. Then, an ultra-energy-efficient interconnect structure is obtained by actively shielding such low-swing lines. The structures under study are simulated comprehensively at the 7-nm technology node. The results indicate that the MLGNR interconnect is significantly more energy efficient than its multiwall carbon nanotube (MWCNT) counterpart in the low-voltage regime. Moreover, the proposed approach is superior to its MLGNR counterparts. The proposed structure leads to 86%, 75%, and 31% lower energy consumption over a length of 500 µm as compared with the typical, actively shielded, and low-swing MLGNR interconnects, respectively. Moreover, the impact of the ratio of the widths of the signal line to the shield line on the performance of the interconnects is evaluated. The energy consumption reduction achieved by the proposed approach is mostly preserved even when using minimum-width shield lines on wider signal lines to reduce the area overhead. Moreover, the impact of process variations on the performance of the interconnects is assessed using Monte Carlo simulations, demonstrating the robustness of the proposed approach.

     

Optimal tuning of linear controllers for power electronics/power systems applications

This paper presents a new method for tuning various linear controllers such as Proportional-Integral (PI), Proportional-Integral-Derivative (PID) and Proportional-Resonant (PR) structures which are frequently used in power electronics and power system applications. The linear controllers maintain a general structure defined by the Internal Model Principle (IMP) of control theory. The proposed method in this paper is twofold. The first perspective uses the well-known concept of the Linear Quadratic Regulator (LQR) to address the problem as a regulation problem. The Q matrix of the LQR design is then finely adjusted in order to assure the desired transient response for the system. The second perspective redefines the LQR in order to add capability to address the optimal tracking problem and is then generalized to systems with more than two states. These methods are then applied to two specific examples, one in an uninterruptible power supply (UPS) inverter system and the other one in a distributed generation (DG) system. In these examples, the tuning of PR and PI controllers is studied in great detail. These proposed design methods provide an easy and algorithmic procedure without jeopardizing stability or robustness. These tuning methods can also be utilized for linear state-space realization of any power converters. Both examples are supported via simulation and the results, which confirm analytical derivations, are presented and discussed.     

A theoretical investigation of the characteristic temperature T/sub 0/ for semiconductor lasers

The temperature dependence of the characteristic temperature T/sub 0/ of semiconductor quantum-well lasers is investigated using detailed simulations. The critical-temperature-dependent processes are the optical gain and the nonradiative recombination. The gain model is based on k /spl middot/ p theory with the multiple quantum wells in the active layer represented by a superlattice. The Auger process is assumed to be thermally activated. It is shown that, with inclusion of the continuum state filling and interband mixing, the most important features experimentally observed in the temperature dependence of the T/sub 0/ value can be explained. The continuum state filling and band nonparabolicity cause a significant deviation from the ideal linear carrier density versus temperature relation for quantum wells. The results are compared to experiment for broad area devices lasing at 980 nm and 1.3, and 1.55 /spl mu/m, and show good agreement over a broad range of temperature.     

Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications

Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.     

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction. Our results indicate that the GPJL MOSFET outperforms the conventional JL MOSFET, yielding higher values of drain current (I _ds), transconductance (g _m), and cutoff frequency (f _t). Further, the emerging electric field and velocity distributions, as a consequence of the channel engineering introduced by the GPJL MOSFET, result in lower output conductance (g _ds) and higher early voltage (V _ea). The preeminence of the GPJL transistor over the JL transistor is further illustrated by showing improvements on the intrinsic voltage gain (A _vo) in the subthreshold regime, to as high as 61 %. These results indicate that our proposed GPJL MOSFET yields improvement in the analog/RF performance metrics as compared to JL MOSFETs.     

Power and energy management of grid/PEMFC/battery/supercapacitor hybrid power sources for UPS applications

This paper presents a hybrid power and energy source supplied by a proton exchange membrane fuel cell (PEMFC) as the main power source in an uninterruptible power supply (UPS) system. To prevent the PEMFC from fuel starvation and degradation and realize their seamless linking in the hybrid UPS system, the power and energy are balanced by the battery and/or supercapacitor (SC) as two alternative auxiliary power sources. Based on the modeling and sizing of hybrid power and energy components, the power and energy management strategies and efficiency measurements of four operating modes in UPS system are proposed. To evaluate the proposed strategies, an experimental setup is implemented by a data acquisition system, a PEMFC generating system, and a UPS system including AC/DC rectifier, DC/AC inverter, DC/DC converter, AC/DC recharger and its intelligent control unit. Experimental results with the characteristics of a 300 W self-humidified air-breathing of PEMFC, 3-cell 12 V/5 Ah of batteries, and two 16-cell 120 F/2.7 V of SCs in parallel corroborate the excellent management strategies in the four operating modes of UPS system, which provides the basis for the optimal design of the UPS system with hybrid PEMFC/battery/SC power sources.     

Studies of a PT/PZT/PT sandwich structure for feram applications using sol-gel processing

Abstract

A silicon-based PbTiO₃/Pb(Zr,Ti)O₃/PbTiO₃ (PT/PZT/PT) sandwich structure with Pt electrodes are prepared by a sol-gel method. Effects of the PT buffer layers to the phase formation of the PZT films are studies. Dielectric and ferroelectric properties of the sandwich structure are measured. Maximum dielectric constant of about 900 is obtained at the coercive field 20 kV/cm. The leakage current density is less than 5 × 10^?9 A/cm2 below 200 kV/cm, which is much lower than that of PZT/PT structure. And there is almost no fatigue even after 5 × 109 read/write cycles for the PT/PZT/PT sandwich structure.