Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.     

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.     

Delta-doped tunnel FET (D-TFET) to improve current ratio ($$I_\mathrm{ON}/I_\mathrm{OFF}$$) and ON-current performance

A two dimensional (2D) analytical drain current model has been developed for a delta-doped tunnel field-effect transistor (D-TFET) that can address the ON-current issues of the conventional TFET. Insertion of a highly doped delta layer in the source region paves the way for improved tunneling volume and thus provides high drain current as compared with TFETs. The present model takes into account the effects of the distance between the delta-doping region and the source–channel interface on the subthreshold swing (SS), current ratio, and ON-current performance. The D-TFET is predicted to have a higher current ratio \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{11}} \right) \) compared with TFETs \(\left( {\frac{I_\mathrm{ON} }{I_\mathrm{OFF} }\cong 10^{10}} \right) \) with a reasonable SS \(\left( {{\sim }52\,\mathrm{mV/dec}} \right) \) and \(V_\mathrm{th}\) performance at an optimal position of 2 nm from the channel. The surface potential, electric field, and minimum tunneling distance have been derived using the solution of the 2D Poisson equation. The accuracy of the D-TFET model is validated using the technology computer aided design (TCAD) device simulator from Synopsys.     

New nanoscale band-to-band tunneling junctionless GNRFETs: potential high-performance devices for the ultrascaled regime

High-performance sub-10-nm field-effect transistors (FETs) are considered to be a prerequisite for the development of nanoelectronics and modern integrated circuits. Herein, new band-to-band tunneling (BTBT) junctionless (JL) graphene nanoribbon field-effect transistors (GNRFETs) endowed with sub-10-nm gate length are proposed using a quantum transport simulation. The nonequilibrium Green’s function (NEGF) formalism is used in quantum simulations considering the self-consistent electrostatics and the ballistic transport limit. The computational assessment includes the I_DS–V_GS transfer characteristics, the potential and electron density distributions, the current spectrum, the ambipolar behavior, the leakage current, the subthreshold swing, the current ratio, and the scaling capability. It is found that BTBT JL-GNRFETs can provide subthermionic subthreshold swings and moderate current ratios for sub-10-nm gate lengths. Moreover, a new doping profile, based on the use of lateral lightly n-type-doped pockets, is adopted to boost their performance. The numerical results reveal that BTBT JL-GNRFETs with the proposed doping profile can exhibit improved performance in comparison with uniformly doped BTBT JL-GNRFETs. In addition, the role of the length and n-type doping concentration of the pockets in boosting the device performance is also studied and analyzed while considering the scaling capability of such devices, revealing that low doping concentrations and long pocket lengths are useful for performance improvement. The merits of the BTBT JL-GNRFETs based on the proposed nonuniform doping profile, namely sub-10-nm scale, steep subthermionic subthreshold swing, low leakage current, and improved current ratio and ambipolar behavior, make them promising nanodevices for use in modern nanoelectronics and high-performance integrated circuits.

     

Numerical Simulation for Direct Tunneling Current in Poly-Si-Gate MOS Capacitors

We have numerically simulated gate tunneling current in MOS capacitors. Price has demonstrated that the Gamow formulation can be applied to analysis of the escape of electrons from channel into gate in MOSFETs [P.J. Price, Appl. Phys. Lett., 82, 2080 (2003)]. We have integrated the Gamow method into a Schrödinger-Poisson solver for metal-gate and poly-Si-gate n-type MOS capacitors. The numerical results of the tunneling current are then compared with experimental results.     

A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

Asymmetric junctionless nanowire TFET with built-in $${n}^{+}$$ source pocket emphasizing on energy band modification

We present a detailed study on a technique to realize a narrow and highly doped built-in \({n}^{+}\) source pocket in an asymmetric junctionless nanowire tunnel field-effect transistor (AJN-TFET). In the proposed structure, a built-in \({n}^{+}\) source pocket is created between the \({p}^{+}\) source and the channel without the need for any separate implantation or epitaxial growth. This leads to band diagram modification by providing a local minimum in the conduction band which results in tunneling width reduction at the source–channel interface in on-state. This leads to an abrupt transition between on- and off-state, improved subthreshold swing (SS) (38 mV/dec), and significant on-current enhancement (\(\sim 2000\) times) at low operating voltage compared with the conventional TFET. We further study the effect of the length of the built-in \({n}^{+}\) source pocket on the AJN-TFET characteristics. The proposed structure overcomes the difficulty in creating a narrow \({n}^{+}\) pocket and thus renders the AJN-TFET device more amenable for the future scaling trend needed in low-power applications.     

Degradation of direct‐tunneling gate oxide under hot hole injection

The degradation of ultrathin SiO₂ films accompanied by the hole direct tunneling is investigated using a substrate hot hole (SHH) injection technique. Hot holes from the substrate as well as cold holes in the inversion layer are injected into the gate oxides in p‐channel MOSFETs with p⁺ poly‐Si gates, while the gate bias is kept low enough to avoid simultaneous electron injection from the gate. During the SHH stress, in contrast to the case of thicker oxide films, a strong correlation is observed between the oxide film degradation and the injected hole energy, whereas no degradation occurs due to the hole direct tunneling from the inversion layer. These experimental findings indicate the existence of threshold energy for trap creation process, which has been predicted by the theoretical study of hole‐injection‐induced structural transformation of oxygen vacancy in SiO₂. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 140(4): 54–61, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.2008     

A 3D analytical modeling of tri-gate tunneling field-effect transistors

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.     

带开关电容网络的交错并联磁集成电感Boost变换器

针对传统交错并联Boost变换器电压增益低、开关管电压应力高、电感电流纹波大等问题,提出一种新型交错并联Boost变换器。该变换器用2个开关电感单元分别代替储能电感L₁和L₂,并对开关电感进行耦合集成,在此基础上增加了1个二极管和2个电容构成开关电容网络。分析了变换器在不同占空比下的工作模态,推导了电压增益公式,分析了开关管电压应力和电感电流纹波的大小。与传统交错并联Boost变换器相比,该变换器性能得到明显提升,尤其在占空比D>0.5的情况下电压增益是传统交错并联Boost变换器的3（1+D）倍,开关管的电压应力减小了2/3,电感电流纹波也减小近一半。最后实验验证了理论分析的正确性。表明带开关电容网络的交错并联磁集成电感Boost变换器有着优良的工作性能。     

Characterization of defect density created by stress in the gate to?drain overlap region using GIDL current model in n-channel MOSFET

In this paper we study the impact of stress on gate induced drain leakage (GIDL) current variations in MOS transistors, which manifested by tunneling in the gate to drain overlap region. The oxide thickness of n-channel transistor used is 8.5?nm. We show that this phenomenon is accentuated in high stress accumulation V _g=?3?V, V _d=3?V, but more less for stress V _g=V _d=3?V. In both cases, any constraint corresponds to an increase in accumulated charges in the transistor and hence the current GIDL.     

Modeling the Inelastic Scattering Effect on the Resonant Tunneling Current

Resonant tunneling current with the inelastic scattering effect is modeled basing on the sequential tunneling approach. Simulations are performed for the case of a silicon double gate (n⁺)polySi/SiO₂/(i)Si/SiO₂/(n⁺)polySi structure     

Interface potential barrier height and leakage current behavior of Pt/(Ba,Sr)TiO3/Pt capacitors fabricated by sputtering process

Abstract

Variations of the leakage current behaviors and interface potential barrier height (φ _B ) of rf-sputter deposited (Ba, Sr)TiO₃ (BST) thin films, with thickness ranging from 20nm to 150 nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. φ _B critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under N₂ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the φ _B from about 2.4 eV to 1.6eV due to the oxidation. φ _B is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20nm thick film shows tunneling current, 30 and 40 nm thick films show Schottky emission current and the thicker films show a mixed characteristics and bulk and interface limited currents although the mechanism is not clearly understood at this moment.     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

Fourth generation MOSFET model and its VHDL‐AMS implementation

While the last decade has been dominated by Berkeley's BSIM3 and BSIM4 models (third generation models), a new type of compact models like HiSIM, SP, MM11 or EKV3 is more and more accepted in the semiconductor industry. These new models are either surface‐potential‐based models or charge linearization models (EKV3) and, as a result, should be regarded as the fourth generation of MOSFET models. Based on the core of the MM11 model, we have developed new concepts to compute the exact value of the surface potential, i.e. accounting for the quantum effects. The model covers all operating regions from accumulation to inversion and is valid for all bias conditions. The VHDL‐AMS implementation of the model is then demonstrated and a representative set of simulation results is presented. The computation of charges, transcapacitances and drain current shows an excellent behaviour in terms of accuracy and speed, while requiring no additional parameter in comparison to a classical model. Comparison with experimental data from a current deep‐submicron technology is also provided. Copyright © 2004 John Wiley & Sons, Ltd.     

INDUCTION MOTOR DRIVE STABILIZATION WITH STATOR CURRENT FEEDBACK

ABSTRACT

The use of state feedback to control Induction motor drive systems is examined. Using the machine currents and speed as the system states, a general linearized formulation of the problem is derived. This formulation has the advantages of previous forms based on complex variable analysis, but is not subject to the limitations of that method.

The proposed model Is used to study machine control with stator current feedback. The results show that stator current feedback can be used to improve the dynamic characteristics of the drive system. Comparisons of stator current control with the uncontrolled machine and with the slip controlled machine are presented over the range of operating speed, load, and inertia. In all cases, advantages of current controlled operation can be seen.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

A new analytical model for the gate threshold voltage (\(V_\mathrm{TG}\)) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson’s equation in the lightly doped Si film and employing the physical definition of \(V_\mathrm{TG}\). A numerical simulation study of the transfer characteristics and \(V_\mathrm{TG}\) of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of \(V_\mathrm{TG}\) is performed based on the transconductance change method as already used for conventional metal–oxide–semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on \(V_\mathrm{TG}\) are reported. The dependence of \(V_\mathrm{TG}\) on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.     

An optimal algorithm for rectilinear steiner trees for channels with obstacles

The channel rectilinear Steiner tree problem is to construct an optimal rectilinear Steiner tree interconnecting n terminals on the upper shore and the lower shore of a channel without crossing any obstacles inside the channel. However, intersecting boundaries of obstacles is allowed. We present an algorithm that computes an optimal channel rectilinear Steiner tree in O(F₁(k)n + F₂(k)) time, where k is the number of obstacles inside the channel and F₁ and F₂ are exponential functions of k. For any constant k the proposed algorithm runs in O(n) time.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.