Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Efficient and reliable fault analysis methodology for nanomagnetic circuits

The increasing issues in scaled Complementary Metal Oxide Semiconductor (CMOS) circuit fabrication favor the flourishing of emerging technologies. Because of their limited sizes, both CMOS and emerging technologies are particularly sensitive to defects that arise during the fabrication process. Their impact is not easy to analyze in order to take the necessary countermeasures, especially in the case of circuits of realistic complexity based on emerging technologies. In this work, we propose a new methodology supported by an efficient and reliable tool for the identification of the impact of faults in complex circuits implemented using the emerging technology we are focusing on in this case: nanomagnetic logic. The methodology is based on three main steps: (i) we performed exhaustive physical‐level simulations of basic blocks based on a detailed finite‐element tool in order to have a full characterization, to know their properties in presence of defects, and to have a solid reference point for the following steps; (ii) we developed a model (fanomag ) for the basic block behavior suitable for simulations in presence of defects of complex circuits, that is, lighter than a physical level one, but accurate enough to capture the most important features to be inherited at circuit level; (iii) starting from a physical design of complex circuits that we perform using a specific design tool we developed, that is, ToPoliNano , we simulated using fanomag , now embedded in our ToPoliNano tool, the behavior of circuits in presence of multiple sets of fabrication defects using a Monte Carlo approach now included in ToPoliNano as a new feature. In this paper, a specific type of defect is considered as a case study. The framework and methodology are conceived to be easily extended to handle other types of defects and problems due to working conditions that a designer and/or a technologist might want to focus on. The major outcome is then a powerful methodology and tool capable to analyze with a good accuracy nanomagnetic logic complex circuits and architectures both in ideal conditions and in presence of defects with remarkable performance in terms of simulation times. Copyright © 2016 John Wiley & Sons, Ltd.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of \(0.02\,\upmu \hbox {m}^{2}\) and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.     

三值与非门及四态门开关电路的研究

采用双极型晶体管设计的三值TTL与非门及四态门均属于开关电路．这类门电路可用于构成三值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用．     

A VERIFICATION OF NONVOLATILE PROGRAMMABLE LOGIC DEVICE

ABSTRACT

In this paper, Ferroelectric is introduced to nonvolatile programmable logic device (NVPLD). The device system is constructed, and the circuits of three main elements: switch cell, nonvolatile D flip-flop (NVDFF) and configurable logic block (CLB), are presented. Based on the circuit design, the feasibility of this device has been verified.     

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

Scaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits. Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.     

Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

DQPSK调制系统差分编译码电路的设计与Multisim仿真

差分正交移相键控(DQPSK)是现代宽带无限数字通信的常用调制方式,其中的四进制差分编译码电路是设计的关键。本文通过对DQPSK数字调制解调系统中四进制差分编码器的功能分析,导出其逻辑表达式和真值表,从而设计出四进制差分编码器的逻辑电路图,再用Multisim虚拟电子电路仿真软件验证所设计的电路的功能,结果表明完全符合DQPSK的差分编解码要求。     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

FDSTDL: Low-power technique for FinFET domino circuits

Major issues in designing low-power high-speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field-effect transistor (FinFET) technology for the design of low-power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal-oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2-, 4-, 8-, and 16-input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK-DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse-mesh finite difference (CMFD) technique at a frequency of 200 MHz.     

THREE-DIMENSIONAL ELECTRIC MOTORS

ABSTRACT

The use of simple geometries in engineering (rectangular blocks, cylinders and spheres) has enabled most machines to be described by a few 2-dimensional drawings such as plan, elevation and section. Any given section through a conventional electro-mechanical energy converter normal to its axis is the same as any other parallel section. The design of a conventional electric motor is therefore basically a 2-D design

Early attempts to exploit curvature in the third dimension by using a part spherical motor were unsuccessful but the thinking thereby involved paved the way for linear motor designs in 3-D that were to follow a decade later. In particular, the problem of designing a high speed linear motor fed directly from unprocessed mains supply was solved by turning the magnetic circuits into transverse planes

Further development of Transverse Flux Motors (TFM) showed how lift, guidance and propulsion could be achieved by the use of a single set of primary coils without control equipment. The problem of track expansion joints was also solved by 3-D technology in which the track plates are folded into vertical planes at the joints so as to constitute single-turn current transformers.     

Static and dynamic characteristics of dual gate organic TFT based NAND and NOR circuits

This research paper analyzes the static and dynamic behavior of dual-gate organic thin film transistors (DG-OTFTs) based universal logic gates using the Atlas 2-D numerical device simulator. The electrical characteristics and performance parameters of pentacene based DG-OTFT is evaluated and verified with respect to the reported experimental results. The NAND and NOR logic gate circuits are realized using \(p\) -type designs in diode-load logic (DLL) and zero- \(V_{gs}\) -load logic (ZVLL). The results show that the logic functions in ZVLL configuration outperforms the DLL ones mainly in terms of noise margin, gain and voltage swing; however, there is a trade-off in terms of speed. The ZVLL NAND gate demonstrates an increment of 16 and 32 % in voltage swing and noise margin, respectively in comparison to the DLL one. Besides this, the gain also increases by 1.5 times in ZVLL mode. On the contrary, the DLL configuration demonstrates a significant reduction of 64 % in the propagation delay in comparison to the ZVLL. Similarly, NOR gate shows an increment of 24 and 30 % in voltage swing and noise margin, respectively under ZVLL configuration. However, the propagation delay for DLL NOR configuration is one-fourth of that of its ZVLL counterpart.     

Threshold voltage extraction techniques adaptable from sub‐micron CMOS to large‐area oxide TFT technologies

This paper proposed simple and accurate threshold voltage (V _TH ) extraction techniques, which can be directly adaptable to various semiconductor technologies ranging from deep sub‐micron complementary metal–oxide–semiconductor to large‐area thin‐film transistor devices. These techniques are developed using multiple circuits, namely, a dynamic source follower, an inverter with a diode‐connected load and a current mirror topology, which allow a direct determination of V _TH . As the proposed techniques are experimented with large‐area emerging technologies, which have a stable single type (n‐type) transistor, all the designs employed in this work are confined to only n‐type transistors for a fair comparison. The semiconductor technologies under consideration are standard complementary metal–oxide–semiconductor (65 and 130 nm) and oxide (indium–gallium–zinc–oxide and zinc–tin–oxide) thin‐film transistors. In order to validate the accuracy of the proposed techniques, extracted V _TH from these methods are compared against the value from linear transfer characteristics. The resulting relative error is within 5%, reinforcing proposed techniques suitability to different semiconductor technologies ranging from deep sub‐micron to large‐area transistors. Copyright © 2017 John Wiley & Sons, Ltd.     

Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

Binary decision diagrams (BDDs) are the most frequently used data structure for the representation and handling of Boolean functions because of their excellent time and space efficiencies. In this article, a reversed BDD‐based pass transistor logic (PTL) logic synthesis is presented for low‐power and high‐performance circuits without exploiting the canonical property of BDDs. The procedure of the reversed BDD transformation into PTL is achieved by a one‐to‐one correspondence with the BDD node and PTL cell. Layouts are generated for the benchmark circuits and simulated in terms of power dissipation, propagation delay and area. The reversed BDD technique performs better in terms of area, delay and power dissipation due to the regularity, a reduced critical path, less interconnection wires, a multiplexer‐based construction of PTL circuits, and less switching activities. Copyright © 2011 John Wiley & Sons, Ltd.     

The design,analysis, and cost estimation of a generic adder and subtractor using the layered T (LT) logic reduction methodology with a quantum-dot cellular-automata-based approach

The quantum-dot cellular automata (QCA) is considered to be one of the ground-breaking nanotechnologies developed over the last two decades. A layered T (LT) logic cell library is constructed herein, and the methodology is extended to generic adder and subtractor module designs. The two proposed algorithms lead to more efficient QCA layout designs for an n-bit ripple carry adder (RCA) and subtractor based on an effective clock zone assignment approach. The suggested one-, four-, and eight-bit RCAs and subtractors surpass most of their existing counterparts by offering lower effective area and cell complexity. A comparative analysis is presented regarding the complexity, irreversible power dissipation, and Cost_α of the proposed n-bit layouts from a cost estimation purview.

     

An ultra-energy-efficient crosstalk-immune interconnect architecture based on multilayer graphene nanoribbons for deep-nanometer technologies

An ultra-energy-efficient interconnect structure based on multilayer graphene nanoribbon (MLGNR) interconnects for deep-nanometer technologies is proposed herein. First, a low-swing interconnect based on MLGNRs and high-performance interface circuits using carbon nanotube field-effect transistors (CNTFETs) is proposed. Then, an ultra-energy-efficient interconnect structure is obtained by actively shielding such low-swing lines. The structures under study are simulated comprehensively at the 7-nm technology node. The results indicate that the MLGNR interconnect is significantly more energy efficient than its multiwall carbon nanotube (MWCNT) counterpart in the low-voltage regime. Moreover, the proposed approach is superior to its MLGNR counterparts. The proposed structure leads to 86%, 75%, and 31% lower energy consumption over a length of 500 µm as compared with the typical, actively shielded, and low-swing MLGNR interconnects, respectively. Moreover, the impact of the ratio of the widths of the signal line to the shield line on the performance of the interconnects is evaluated. The energy consumption reduction achieved by the proposed approach is mostly preserved even when using minimum-width shield lines on wider signal lines to reduce the area overhead. Moreover, the impact of process variations on the performance of the interconnects is assessed using Monte Carlo simulations, demonstrating the robustness of the proposed approach.

     

数字式有源电力滤波技术中谐波电流补偿分量的检测

为提高有源电力滤波器(Active Power Filter,APF)的补偿性能,以理想传输量分离法为理论基础,提出了一种基于现场可编程逻辑阵列(Field Programmable Gate Array,FPGA)器件和快速模/数转换(A/D)的数字式有源电力滤波技术中谐波电流补偿分量的检测方法。该方法通过配置FPGA器件的时钟、逻辑运算电路以及静态存储器来实现A/D转换控制以及补偿分量的计算。与常规的基于数字信号处理程序的检测方法相比,该方法有效地利用了FPGA器件的并行运算以及近似布线逻辑的电路特点,提高了APF的抗干扰能力及补偿性能。仿真和实验结果表明,采用该检测方法的APF具有更好的实时性、准确性和抗干扰能力。     

Evaluation of Chemical Solution Deposited Ba x Sr 1−x TiO 3 Thin Films on LaAlO 3 in Tunable Microwave Devices

Epitaxial Ba x Sr 1 m x TiO 3 (BST) films grown on LaAlO 3 by several deposition methods have been tested in coupled microstrip phase shifters (CMPS) at frequencies from 10 to 24 GHz. To date the best performance for the devices has been achieved using Pulsed Laser Deposition (PLD). However, recently chemical solution deposition (CSD) methods such as sol-gel and Metal-Organic Chemical Liquid Deposition (MOCLD) have shown advances in fabricating BST films for tunable microwave applications. CSD processes promise improvements in cost, speed and area covered during BST film deposition. This paper compares over 35 BST films used in identical CMPS circuits. In this study, the highest measured figures of merit of phase shift per dB of loss for PLD, MOCLD and sol-gel CMPS are 49, 47 and 41°/dB respectively. While other phase shifter designs using BST films have surpassed these values, these data base of identical circuits allows us to compare the BST films. X-ray diffraction characterization for many of the BST films is also given.     

Optimal sizing and design of CMOS analogue amplifier circuits using craziness‐based particle swarm optimization

This paper presents the optimal designs of two analogue complementary metal–oxide–semiconductor (CMOS) amplifier circuits, namely differential amplifier with current mirror load and two‐stage operational amplifier. A modified Particle Swarm Optimization (PSO), called Craziness‐based Particle Swarm Optimization (CRPSO) technique is applied to minimize the total MOS area of the designed circuits. CRPSO is a highly modified version of conventional PSO, which adopts a number of random variables and has a better and faster exploration and exploitation capability in the multidimensional search space. Integration of craziness factor in the fundamental velocity term of PSO not only brings diversity in particles but also pledges convergence close to global best solution. The proposed CRPSO‐based circuit optimization technique is reassured to be free from the intrinsic disadvantages of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS), Artificial Bee Colony (ABC) and Particle Swarm Optimization (PSO). The simulation results achieved for the two analogue CMOS amplifier circuits establish the efficacy of the proposed CRPSO‐based approach over those of DE, HS, ABC and PSO in terms of convergence haste, design conditions and design goals. The optimally designed analogue CMOS amplifier circuits occupy the least MOS area and show the best performance parameters like gain and power dissipation, in compared with the other reported literature. Copyright © 2016 John Wiley & Sons, Ltd.