Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS \(^{\text{ TM }}\) , a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.     

A novel high-performance H-gate U-channel junctionless FET

A novel high-performance H-shape-gate U-shape-channel junctionless FET (HGUC JL FET) is proposed. Compared with the saddle junctionless FET, the proposed HGUC JL FET shows better subthreshold characteristics and higher on-current. Its electrical properties were extensively investigated by studying the influence of variation of design parameters such as the H-gate thickness, the source/drain extension region height, and the gate oxide thickness and material. Compared with conventional structures, the proposed HGUC JL FET shows better performance, especially on scaling down to several nanometers. The reverse leakage current is also effectively restrained and the \({I}_{\mathrm{on}}\)/\({I}_{\mathrm{off}}\) ratio greatly improved through design optimization.     

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the \(\hbox {SiO}_{2}\) dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by \(+\) 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.     

Scalability and process induced variation analysis of polarity controlled silicon nanowire transistor

In this paper, we present scalability and process induced variation analysis of polarity gate silicon nanowire field-effect transistor. 3D simulation results show that the PGFET offers significant reduction in short channel effects and variability due to utilization of uniform lightly doped silicon nanowire (SiNW) as compare to highly doped silicon nanowire in junctionless transistors. The performance parameters were evaluated for different device geometries, such as variation in SiNW radius, equivalent oxide thickness, channel length and spacer length. Sensitivity analysis shows that the PGFET exhibits less dependence towards gate length in comparison to other device parameters. It is seen that ON to OFF current ratio variation with silicon nanowire thickness is lower for PGFET as compared to JLFET. The threshold voltage roll-off and sensitivity towards intrinsic delay in PGFET is much lower than its counterpart device.     

A new two-dimensional analytical subthreshold behavior model for submicron Triple Material Gate (TM) GaN MESFET

A new two-dimensional (2D) analytical model for a Triple Material Gate (TM) GaN MESFET has been proposed and modeled to suppress the short channel effects and improve the subthreshold behavior. The analytical model is based on a two-dimensional analysis of the channel potential, threshold voltage and subthreshold swing factor for TM GaN MESFET is developed. The aim of this work is to demonstrate the improved subthreshold electrical performances exhibited by TM GaN MESFET over dual material gate and conventional single material gate MESFET. The results so obtained are verified and validated by the good agreement found with the 2D numerical simulations using the ATLAS device simulation software. The models developed in this paper will be very helpful to understand the device behavior in subthreshold regime for future circuit applications.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

New nanoscale band-to-band tunneling junctionless GNRFETs: potential high-performance devices for the ultrascaled regime

High-performance sub-10-nm field-effect transistors (FETs) are considered to be a prerequisite for the development of nanoelectronics and modern integrated circuits. Herein, new band-to-band tunneling (BTBT) junctionless (JL) graphene nanoribbon field-effect transistors (GNRFETs) endowed with sub-10-nm gate length are proposed using a quantum transport simulation. The nonequilibrium Green’s function (NEGF) formalism is used in quantum simulations considering the self-consistent electrostatics and the ballistic transport limit. The computational assessment includes the I_DS–V_GS transfer characteristics, the potential and electron density distributions, the current spectrum, the ambipolar behavior, the leakage current, the subthreshold swing, the current ratio, and the scaling capability. It is found that BTBT JL-GNRFETs can provide subthermionic subthreshold swings and moderate current ratios for sub-10-nm gate lengths. Moreover, a new doping profile, based on the use of lateral lightly n-type-doped pockets, is adopted to boost their performance. The numerical results reveal that BTBT JL-GNRFETs with the proposed doping profile can exhibit improved performance in comparison with uniformly doped BTBT JL-GNRFETs. In addition, the role of the length and n-type doping concentration of the pockets in boosting the device performance is also studied and analyzed while considering the scaling capability of such devices, revealing that low doping concentrations and long pocket lengths are useful for performance improvement. The merits of the BTBT JL-GNRFETs based on the proposed nonuniform doping profile, namely sub-10-nm scale, steep subthermionic subthreshold swing, low leakage current, and improved current ratio and ambipolar behavior, make them promising nanodevices for use in modern nanoelectronics and high-performance integrated circuits.

     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

Two-dimensional modeling of subthreshold current and subthreshold swing of double-material-gate (DMG) strained-Si (s-Si) on SGOI MOSFETs

The present paper proposes the surface potential based two-dimensional (2D) analytical models of subthreshold current and subthreshold swing of nanoscale double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The surface potential expression has been directly taken from our previous reported work. The effect of various device parameters on subthreshold current and swing like Ge mole fraction, Si film thickness, gate-length ratio and various combinations of control/screen gate work-functions have been discussed. The validity of the present 2D model is verified by using ATLAS^TM, a 2D device simulator from Silvaco.     

Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures

In this paper, both the forward and reverse characteristics of junctionless (JL) FinFETs with deep nanoscale design parameters have been studied through TCAD device simulation by considering band-to-band tunneling. Design optimization of the JL TG FinFETs has been performed by investigating the influence of the variations of design parameters such as body doping, channel length, body thickness, fin height and gate oxide thickness. The performance difference between the DG and TG JL FinFETs also has been compared by considering the structure difference. The scheme of device optimization has been proposed.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior \(I_{{\textit{ON}}}/I_{{\textit{OFF}}}\) ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.     

Full-Band Particle-Based Analysis of Device Scaling for 3D Tri-Gate FETs

In this work, a 25 nm gate length three-dimensional tri-gate SOI FET with a wrap around gate geometry is studied using a full-band particle-based simulation tool. The tri-gate FETs have shown superior scalability over planar device structures, reduction of short channel effects, higher drive currents and excellent gate-channel controllability compared to their planar counterparts. Simulations were performed by scaling the length and the width of the tri-gate SOI FET channel to study its short-channel and short-width effects. The influence of the scaling on the dynamic response has also been explored by performing a frequency analysis on the device.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Subthreshold behavior optimization of nanoscale Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET using?multi-objective genetic algorithms

In this paper, a multi-objective genetic algorithms-based approach is proposed to study and optimize the subthreshold behavior of Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET for nanoscale CMOS digital applications. The subthreshold parameters such as threshold voltage, drain induced barrier lowering (DIBL), subthreshold swing and OFF-current have been ascertained and mathematical models have been proposed. The proposed mathematical models are used to formulate the objectives functions, which are the pre-requisite of genetic algorithm. The overall objective function is formulated by means of weighted sum approach. Thus, the proposed approach is used to search for optimal subthreshold parameters to obtain better electrical performances of the devices for digital application.     

A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs

The Gate All Around (GAA) MOSFET is considered as one of the most promising devices for downscaling below 50?nm. By surrounding the channel completely, the gate gains increased electrostatic control of the channel and short-channel-effects (SCEs) can be drastically suppressed. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the long-term stability of subthreshold performances in a nanoscale MOS transistor. In this paper we present a two-dimensional analytical analysis of the subthreshold behavior, subthreshold current and subthreshold swing, including the interfacial hot-carrier effects. The calculated results of the proposed approach match well with those of the 2-D numerical device simulator. The present work provides valuable design insights in the performance of nanoscale CMOS-based devices including hot-carrier degradation effects.