非晶硅薄膜太阳电池的数值优化研究

基于Sentaurus TCAD数值分析平台,采用非晶硅的DOS模型对禁带中缺陷态进行表征,建立a-Si:H薄膜太阳电池的二维数值模型。对P-I-N结构的非晶硅太阳电池的本征区、P型区、N区以及P/I界面的特性进行研究,得到参数与薄膜太阳电池性能之间的关系。通过电池物理和结构参数的优化,在界面处引入ZnO作为反射层,优化得到太阳电池填充因子为74.7%,AM1.5下光电转换效率为10.1%,表明采用TCAD数值仿真可有效用于非晶硅太阳电池本征参数和反射层的优化设计,提高电池转换效率。     

Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications

In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by \({\sim }\)900 %), subthreshold swing characteristics (by \({\sim }\)12 %) and Drain Induced Barrier Lowering (DIBL) (by \({\sim }\)56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

A comprehensive two dimensional analytical study of a nanoscale linearly graded binary metal alloy gate cylindrical junctionless MOSFET for improved short channel performance

Over the years, the approach of cylindrical gate MOSFETs has attracted several research initiatives due to the very inherent benefit of the cylindrical geometry over other conventional planar structures. Nowadays, the present boon in the research field of nanoscale device physics is attributed to a large extent by the development of junctionless devices. In our current research endeavor, we have for the first time proposed a new idea by incorporating the innovative concept of work function engineering by the continuous horizontal variation of mole fraction in a binary metal alloy gate into a junctionless cylindrical gate MOS structure, thereby presenting a new device structure, a junctionless work function engineered gate cylindrical gate MOSFET (JL WFEG CG MOSFET). We have presented a rigorous analytical modeling of the proposed JL WFEG CG MOS structure by solving the two dimensional Poisson’s equation in cylindrical co-ordinates. Based on this analytical modeling, an overall performance comparison of the proposed JL WFEG CG MOS and normal JL CG MOS structure has been investigated in order to testify the improved performance of the proposed JL WFEG CG structure over its normal JL CG equivalent in terms of reduced short channel effects, threshold voltage roll off, drain induced barrier lowering and superior current driving capability. The results obtained from our analytical analysis are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

Performance enhancement using forward error correction on powerline communication channels

The use of forward error correction (FEC) coding is investigated, to enhance communication throughput and reliability on noisy power line networks. Rate one-half self-orthogonal convolutional codes are considered. These codes are known to be effective in other environments, and can be decoded inexpensively in real-time using majority logic decoders. Extensive bit and packet error rate tests were conducted on actual, noisy in-building power line links. Coding gains of 15 dB were observed at 10^-3 decoded bit error rates. A self-orthogonal (2, 1, 6) convolutional code with interleaving to degree 7 was particularly effective, and was implemented as a VLSI microelectronic chip. Its use improved data throughput and packet error rates substantially, at data transmission rates of 9,600 bits/s     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Charge storage in double layers of thermally grown silicon dioxideand APCVD silicon nitride

Experimental results on charge storage and discharge in double layers of silicon dioxide and silicon nitride will be reported and discussed. SiO₂ with a thickness of 300 nm was thermally grown on silicon wafers, while cover layers of Si₃N₄ with thicknesses of 50, 100, and 150 nm were deposited chemically at atmospheric pressure. The samples were charged by the point-to-grid corona method. At room temperature, the measured surface potential V was stable during a period of almost three years. Isothermal measurements under different environmental conditions showed an improved charge retention compared to a single layer grown silicon dioxide. After ~3 h at 300°C, the observed voltage drop was <10% for the double layers and ~60% for bare SiO₂. Similar results were obtained under a humid condition of 95%RH and 60°C. Besides, thermally stimulated current (TSC) was measured in setup with a temperature ramp of 200°C/h. For the double layers, a current peak with a maximum temperature at ~500°C was observed. The measured current in the range of 300 to 400°C, the location of current maxima observed in thermally grown silicon dioxide or APCVD silicon nitride, was negligible. In addition to improved electret properties the internal stress in the investigated double layers can be adjusted by a proper thickness ratio of oxide layer to nitride layer. Therefore double layers of silicon dioxide and nitride seem to be promising materials for integrated sensors and actuators based on the electret effect     

Monte Carlo simulation of double gate MOSFET including multi sub-band description

A new two-dimensional self-consistent Monte-Carlo simulator including the multi sub-band transport in a 2D electron gas is described and applied to an ultra-thin Double Gate MOSFET. This approach takes into account both out of equilibrium transport and quantization effects. This method improves significantly microscopic insight into the operation of deep sub-100 nm CMOS devices. We analyze the ballistic, quantization and roughness effects in a 12 nm-long DGMOS transistor. In particular, we focus on the link between non-stationary transport and the evolution of sub-band occupancy along the channel.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Monte Carlo simulation of low-field mobility in strained double gate SOI transistors

Electron transport in strained double gate silicon on insulator transistors has been studied by Monte Carlo method. Poisson and Schroedinger equations have been self-consistently solved in these devices for different silicon layer thicknesses both for unstrained and strained silicon channels. The results show that the strain of the silicon layer leads to a larger population of the no-primed subbands, thus decreasing the average conduction effective mass. However, strain also contributes to a larger confinement of the charge close to the two Si/SiO₂ interfaces, thus weakening the volume inversion effect, and limiting the potential increase of the phonon limited mobility.     

Physical modeling of electron mobility enhancement for arbitrarily strained silicon

The band structure of Silicon under arbitrary stress/strain conditions has been calculated using the empirical non-local pseudopotential method. It is shown that the change of the electron effective mass cannot be neglected for general stress conditions and how this effect together with the strain induced splitting of the conduction bands can be used to optimize the electron mobility. The effective mass change has been incorporated into our Monte Carlo simulator VMC and an existing low-field mobility model.