Sb-modified growth of stacked Ge/Si(100) quantum dots

We report on the Sb induced modifications of the morphology of self assembled Ge/Si(100) quantum dot stacks in a Si matrix grown by a molecular beam epitaxy. It is shown that the size of the quantum dots in the stack and the Si spacer layer uniformity inside the stack are regulated by the amount of deposited Sb. We consider the thin Sb layer at the Ge/Si growth interface as a factor limiting the surface migration of Si and Ge ad-atoms. The surface diffusion coefficients of Si ad-atom on uncovered pyramid shaped Ge island and on a Ge island covered by a single monolayer of Sb are estimated to be 2.4 μm²s⁻¹ and 2.3 × 10⁻⁴ μm²s⁻¹ at a temperature of 600 °C, correspondingly. Based on this remarkable reduction of surface diffusion the morphology of the surface can be preserved when the growth is continued after the single monolayer of Sb is at the surface.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.     

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.     

Epitaxial growth of relaxed germanium layers by reduced pressure chemical vapour deposition on (110) and (111) silicon substrates

The growth of Ge on (110) and (111) oriented Si substrates is of great interest to enhance the mobility of both holes and electrons in complementary metal oxide semiconductor transistors. However, the quality of thick, relaxed Ge layers grown epitaxially on these surfaces is usually much lower than similar layers grown on (100) Si, resulting in both higher defect densities (i.e. threading dislocations and stacking faults) and rougher surfaces. In this work we have investigated the growth of Ge layers on (110) and (111) Si substrates by reduced-pressure chemical vapour deposition using a two temperature process. We have found that the combination of suppressing the Ge seed layer roughness and high temperature post-growth annealing can reduce the rms surface roughness of (110) Ge layers to below 2 nm and the threading dislocation density to below 1 × 10⁷ cm^− 2. Thick (111) Ge layers were found to exhibit a very high density of stacking faults, that could not be reduced by post-growth annealing and a higher rms surface roughness of around 12 nm, which was limited by the Ge seed layer.     

Different shape of GaAs quantum structures under various growth conditions

We report the influences of growth parameters on the characteristics of GaAs quantum rings (QRs) and quantum dots (QDs) formed on AlGaAs/GaAs by the droplet epitaxy (DE) method. After forming Ga droplets on the AlGaAs/GaAs surface, varying amounts of arsenic (As) flux were introduced to fabricate the GaAs quantum structures. By decreasing the As flux from 8 × 10^− 5 to 3 × 10^− 5 Torr, the shape of the GaAs quantum structures was changed from QDs to elongated QRs. With further decreasing As flux, the shape of the elongated QRs became symmetric. The formation characteristics of the GaAs QRs from the QDs with the amount of As flux were discussed in terms of migration behaviors of the gallium (Ga) atoms on the GaAs(001)-c(4 × 4) surface. The effects of the amount of Ga supply and the growth temperature for the deposition of Ga droplets on the formation of the GaAs quantum structures were also considered.     

Removal of stacking faults in Ge grown on Si through nanoscale openings in chemical SiO2

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO₂ template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (?10⁶ cm^− 2). This result compares favorably to a threading dislocation density exceeding 10⁸ cm^− 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10⁷ cm^− 2), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO₂ not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10⁷ cm^− 2, but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO₂ has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10⁷ cm^− 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO₂ template and subsequently improve the quality of Ge film.     

Electrical characterization of high-k gate dielectrics on Ge with HfGeN and GeO2 interlayers

Two kinds of HfSiO_x/interlayers (ILs)/Ge gate stack structures with HfGeN- and GeO₂-ILs were fabricated using electron cyclotron resonance (ECR) plasma sputtering and the subsequent post deposition annealing (PDA). It was found that HfGe was formed by the deposition of Hf metal on Ge and changed to HfGeN by N₂ ECR-plasma irradiation, which was used as IL. Another IL was GeO₂, which was grown by thermal oxidation at 500 °C. For dielectrics with HfGeN-IL, PDA of 550 °C resulted in effective oxide thickness (EOT) of 2.2 nm, hysteresis of 0.1 V, and interface state density (D_it) = 7 × 10¹² cm^− 2 eV^− 1. For dielectrics with GeO₂-IL, PDA of 500 °C resulted in EOT of 2.8 nm, hysteresis of 0.1 V, and D_it = 1 × 10¹² cm^− 2 eV^− 1. The structural change of HfSiO_x/GeO₂/Ge during the PDA was clarified by using X-ray photoelectron spectroscopy, and the gate stack formation for obtaining the good IL was discussed.     

Structural and optical properties of ultrananocrystalline diamond / InGaAs/GaAs quantum dot structures

The combination of the unique properties of ultrananocrystalline diamond (UNCD) films and of semiconductor quantum dot (QD) structures could significantly improve the performance of different electronic and optoelectronic devices, where e.g. good thermal management and advanced mechanical parameters are required. In the current work quantum dot InGaAs/GaAs heterostructures have been grown by molecular beam epitaxy (MBE) with different densities between 1.6 × 10¹⁰ cm^− 2 and 1.6 × 10¹¹ cm^− 2 controlled by the substrate temperature in the range between 490 and 515 °C. These structures were overgrown with UNCD by microwave plasma chemical vapor deposition (MWCVD) using methane/nitrogen mixtures at 570 °C. Scanning electron microscopy (SEM) reveals that without ultrasonic pretreatment the diamond nucleation density on QD structures is low and only separate islands of UNCD are deposited, while after pretreatment thin closed films are formed. From the cross-section SEM images a growth rate of ca. 3 nm/min is estimated which is very close to that on silicon at the same deposition conditions. The UNCD coatings exhibit a morphology consisting of two types of structures as shown by atomic force microscopy (AFM). The first one includes nodules with diameters between 180 and 350 nm varying with the density of the underlying QDs; the second is formed by a kind of granular substructure of these nodules with diameters of about 40 nm for all QD densities. The optical properties were investigated by photoluminescence (PL) spectroscopy before and after the deposition of UNCD. The PL signals of QD structures overgrown with UNCD, although with decreased intensity, remain almost unchanged with respect to the peak positions and widths, revealing that the UNCD/QD structures retain the optical properties of uncoated InGaAs/GaAs quantum dots.     

Growth and characterization of germanium nanowires by electron beam evaporation

Germanium nanowires were grown on Au coated Si substrates at 380 °C in a high vacuum (5 × 10^− 5 Torr) by e-beam evaporation of Germanium (Ge). The morphology observation by a field emission scanning electron microscope (FESEM) shows that the grown nanowires are randomly oriented with an average length and diameter of 600 nm and 120 nm respectively for a deposition time of 60 min. The nanowire growth rate was measured to be ∼ 10 nm/min. Transmission electron microscope (TEM) studies revealed that the Ge nanowires were single crystalline in nature and further energy dispersive X-ray analysis (EDAX) has shown that the tip of the grown nanowires was capped with Au nanoparticles, this shows that the growth of the Ge nanowires occurs by the vapour liquid solid (VLS) mechanism. HRTEM studies on the grown Ge nanowire show that they are single crystalline in nature and the growth direction was identified to be along [110].     

Extended deep level defects in Ge-condensed SiGe-on-Insulator structures fabricated using proton and helium implantations

SiGe-on-Insulator (SGOI) structures were created using the Ge condensation method, where an oxidation process is performed on the SiGe/Si structure. This method involves rapid thermal chemical vapor deposition and H⁺/He⁺ ion-implantations. Deep level defects in these structures were investigated using deep level transient spectroscopy (DLTS) by varying the pulse injection time. According to the DLTS measurements, a deep level defect induced during the Ge condensation process was found at 0.28 eV above the valence band with a capture cross section of 2.67 × 10^− 17 cm², two extended deep levels were also found at 0.54 eV and 0.42 eV above the valence band with capture cross sections of 3.17 × 10^− 14 cm² and 0.96 × 10^− 15 cm², respectively. In the SGOI samples with ion-implantation, the densities of the newly generated defects as well as the existing defects were decreased effectively. Furthermore, the Coulomb barrier heights of the extended deep level defects were drastically reduced. Thus, we suggest that the Ge condensation method with H⁺ ion implantation could reduce deep level defects generated from the condensation and control the electrical properties of the condensed SiGe layers.     

Germanium on insulator near-infrared photodetectors fabricated by layer transfer

We report on novel pn Ge photodetectors fabricated on glass. The fabrication consists of wafer bonding and layer splitting, followed by a low-temperature epitaxial growth of Ge. The photodiodes are characterized in terms of dark current and responsivity, and their performance compared with devices realized on either Ge or Si. The minimum current density is 50 μA/cm² at 1 V reverse bias, the responsivity is 0.2 A/W in the photovoltaic mode, with a maximum of 0.28 A/W at 1.55 μm at a reverse voltage of 5 V.     

High quality Ge epitaxial layers on Si by ultrahigh vacuum chemical vapor deposition

Flat, relaxed Ge epitaxial layers with low threading dislocation density (TDD) of 1.94 × 10⁶ cm^− 2 were grown on Si(001) by ultrahigh vacuum chemical vapor deposition. High temperature Ge growth at 500 °C on 45 nm low temperature (LT) Ge buffer layer grown at 300 °C ensured the growth of a flat surface with RMS roughness of 1 nm; however, the growth at 650 °C resulted in rough intermixed SiGe layer irrespective of the use of low temperature Ge buffer layer due to the roughening of LT Ge buffer layer during the temperature ramp and subsequent severe surface diffusion at high temperatures. Two-dimensional Ge layer grown at LT was very crucial in achieving low TDD Ge epitaxial film suitable for device applications.     

Low threading dislocation Ge on Si by combining deposition and etching

Blanket and selective Ge growth on Si is investigated using reduced pressure chemical vapor deposition. To reduce the threading dislocation density (TDD) at low thickness, Ge deposition with cyclic annealing followed by HCl etching is performed. In the case of blanket Ge deposition, a TDD of 1.3 × 10⁶ cm^− 2 is obtained, when the Ge layer is etched back from 4.5 μm thickness to 1.8 μm. The TDD is not increased relative to the situation before etching. The root mean square of roughness of the 1.8 μm thick Ge is about 0.46 nm, which is of the same level as before HCl etching. Further etching shows increased surface roughness caused by non-uniform strain distribution near the interface due to misfit dislocations and threading dislocations. The TDD also becomes higher because the etchfront of Ge reaches areas with high dislocation density near the interface. In the case of selective Ge growth, a slightly lower TDD is observed in smaller windows caused by a weak pattern size dependence on Ge thickness. A significant decrease of TDD of selectively grown Ge is also observed by increasing the Ge thickness. An about 10 times lower TDD at the same Ge thickness is demonstrated by applying a combination of deposition and etching processes during selective Ge growth.     

Nanoscale interfacial engineering to grow Ge on Si as virtual substrates and subsequent integration of GaAs

We have demonstrated the scalability of a process previously dubbed as Ge “touchdown” on Si to substantially reduce threading dislocations below 10⁷/cm² in a Ge film grown on a 2 inch-diameter chemically oxidized Si substrate. This study also elucidates the overall mechanism of the touchdown process. The 1.4 nm thick chemical oxide is first formed by immersing Si substrates in a solution of H₂O₂ and H₂SO₄. Subsequent exposure to Ge flux creates 3 to 7 nm-diameter voids in the oxide at a density greater than 10¹¹/cm². Comparison of data taken from many previous studies and ours shows an exponential dependence between oxide thickness and inverse temperature of void formation. Additionally, exposure to a Ge or Si atom flux decreases the temperature at which voids begin to form in the oxide. These results strongly suggest that Ge actively participates in the reaction with SiO₂ in the void formation process. Once voids are created in the oxide under a Ge flux, Ge islands selectively nucleate within the void openings on the newly exposed Si. Island nucleation and growth then compete with the void growth reaction. At substrate temperatures between 823 and 1053 K, nanometer size Ge islands that nucleate within the voids continue to grow and coalesce into a continuous film over the remaining oxide. Coalescence of the Ge islands is believed to result in the creation of stacking faults in the Ge film at a density of 5 × 10⁷/cm². Additionally, coalescence results in films of 3 µm thickness having a root-mean-square roughness of 8 to 10 nm. We have found that polishing the films with dilute H₂O₂ results in roughness values below 0.5 nm. However, stacking faults originating at the Ge-SiO₂ interface and terminating at the Ge surface are polished at a slightly reduced rate, and show up as 1 to 2 nm raised lines on the polished Ge surface. These lines are then transferred into the subsequent growth morphology of GaAs deposited by metal-organic chemical vapor deposition. Room temperature photoluminescence shows that films of GaAs grown on Ge-on-oxidized Si have an intensity that is 20 to 25% compared to the intensity from GaAs grown on commercial Ge or GaAs substrates. Cathodoluminescence shows that nonradiative defects occur in the GaAs that spatially correspond to the stacking faults terminating at the Ge surface. The exact nature of these nonradiative defects in the GaAs is unknown, however, GaAs grown on annealed samples of Ge-on-oxidized Si, whereby annealing removes the stacking faults, have photoluminescence intensity that is comparable to GaAs grown on a GaAs substrate.     

Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness

Annealing of high-permittivity HfTiO gate dielectric on Ge substrate in different gases (N₂, NH₃, NO and N₂O) with or without water vapor is investigated. Analysis by transmission electron microscopy indicates that the four wet anneals can greatly suppress the growth of a GeO_x interlayer at the dielectric/Ge interface, and thus decrease interface states, oxide charges and gate leakage current. Moreover, compared with the wet N₂ anneal, the wet NH₃, NO and N₂O anneals decrease the equivalent permittivity of the gate dielectric due to the growth of a GeO_xN_y interlayer. Among the eight anneals, the wet N₂ anneal produces the best dielectric performance with an equivalent relative permittivity of 35, capacitance equivalent thickness of 0.81 nm, interface-state density of 6.4 × 10¹¹ eV^− 1 cm^− 2 and gate leakage current of 2.7 × 10^− 4 A/cm² at V_g = 1 V.     

Effects of hydrostatic pressure on Raman scattering in Ge quantum dot superlattices

Self-organized Ge/Si quantum dots (QD's) in strained Si/Ge short-period superlattices are studied by Raman scattering under hydrostatic pressure excited in-resonance and off-resonance with the confined Ge-like E₁ transition of Ge using 488 and 514.5 nm lines from an argon-ion laser and 632.8 nm line from a He-Ne laser. The Raman spectra of Ge-Ge, Si-Ge and Si-2TA modes of the QD's were obtained as a function of pressure in the range of 1-70 kbar. Our results show that the mode Grüneisen parameter of the Ge-Ge phonon mode in QD's is found to be γ=0.81±0.01, which is smaller than that of the bulk Ge. We observe resonance effects with the confined Ge-like E₁ transition and the pressure coefficient of this resonating electronic transition obtained is ∼5±1 meV kbar⁻¹.     

Epitaxy of In0.01Ga0.99As on Ge/offcut Si (001) virtual substrate

In_0.01Ga_0.99As thin films free of anti-phase domains were grown on 7° offcut Si (001) substrates using Ge as buffer layers. The Ge layers were grown by ultrahigh vacuum chemical vapor deposition using ‘low/high temperature’ two-step strategy, while the In_0.01Ga_0.99As layers were grown by metal-organic chemical vapor deposition. The etch-pit counting, cross-section and plane-view transmission electron microscopy, room temperature photoluminescence measurements are performed to study the dependence of In_0.01Ga_0.99As quality on the thickness of Ge buffer. The threading dislocation density of Ge layer was found to be inversely proportional to the square root of its thickness. The threading dislocation density of In_0.01Ga_0.99As on 300 nm thick Ge/offcut Si was about 4 × 10⁸ cm^− 2. Higher quality In_0.01Ga_0.99As can be obtained on thicker Ge/offcut Si virtual substrate. We found that the threading dislocations acted as non-radiative recombination centers and deteriorated the luminescence of In_0.01Ga_0.99As remarkably. Secondary ion mass spectrometry measurement indicated as low as 10¹⁶ cm^− 3 Ge unintended doping in In_0.01Ga_0.99As.     

High performance infra-red detectors based on Si/SiGe multilayers quantum structure

Recently, single crystalline (Sc) Si/SiGe multi quantum structure has been recognized as a new low-cost thermistor material for IR detection. Higher signal-to-noise (SNR) ratio and temperature coefficient of resistance (TCR) than existing thermistor materials have converted it to a candidate for infrared (IR) detection in night vision applications. In this study, the effects of Ge content, C doping and the Ni silicidation of the contacts on the performance of SiGe/Si thermistor material have been investigated. Finally, an uncooled thermistor material with TCR of −4.5%/K for 100 μm × 100 μm pixel sizes and low noise constant (K_1/f) value of 4.4 × 10⁻¹⁵ is presented. The outstanding performance of the devices is due to Ni silicide contacts, smooth interfaces, and high quality multi quantum wells (MQWs) containing high Ge content.     

Nonlinear optical properties of Ag nanocluster composite fabricated by 200 keV negative ion implantation

Metal nanocluster composite glass prepared by 200 keV Ag ions' implantation into silica with dose of 2 × 10¹⁷ ions/cm² has been studied. The formation of sandwiched nanocluster-nanovoid-nanocluster structures has been evidenced by in situ transmission electron microscopy experiment (TEM). Fast nonlinear optical refraction and nonlinear optical absorption coefficients were measured at 532 nm and 1064 nm of wavelength by the Z-scan technique. The third-order nonlinear susceptibility χ⁽³⁾ of this kind of sample was determined to be 4.0 × 10⁻⁸ esu at 532 nm and 9.0 × 10⁻⁸ esu at 1064 nm, respectively.     

Study of the chemical and morphological evolution of InSb(001) surface under low energy ion bombardment

InSb(001) surfaces were subjected to 4 keV Ar⁺ bombardment at oblique angles of incidence with ion fluences in the range of 9.0 × 10¹³-6.2 × 10¹⁷ ions/cm². The evolution of bombardment induced surface structures and their chemical composition were studied with Atomic Force Microscopy (AFM) and Kelvin Probe Force Microscopy (KPFM) in UHV, and “ex situ” with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray spectroscopy (EDX). Various morphological features, such as small dots, wires and for very high ion fluence ripple-like structures were observed. It was found that both the initial surface crystallographic structure and the ion beam direction influence the developing anisotropic nanostructures on the irradiated surface. It was also found that the time evolution of the nanostructured surface in terms of surface roughness σ, follows a power law σ ∼ t^β. The surface nanostructures (dots and wires), at every stage of their development, are found to have different work functions in comparison to the surrounding InSb substrate. The results indicate that the nanostructures developed on the irradiated InSb surfaces consist of indium.