A 16×622 Mb/s ATM switch: PRELUDE switch architectureintegrated into a 6-million transistor monochip

This paper presents the integration of the Prelude switch architecture into a monochip ATM switch, COM16M, capable of handling 16 multiplexes carrying ATM cells at 622 Mb/s. It is a fully autonomous switch, i.e., the chip includes clock adaptation, routing, and cell buffering as well as header translation and control capabilities. The switch is integrated into one single chip containing 6000000 transistors implemented in a 0.5-μm CMOS process     

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

Advanced architecture for a one-chip 16×16 digital switch

A one-chip 16×16 digital switch (SWEL) is presented which is designed for use in a wide variety of applications, ranging from digital mobile radio and satellite applications, to PCM switching systems (integrated services digital network). It provides a compact, low-power solution to perform in channel-controlled switching of 64-kb/s or 2-Mb/s channels. Both architecture and design issues are discussed in detail; a 1.2 μm double metal CMOS technology was employed in the design. The multiplexed architecture allows for easy implementation of new application-specific requirements, making this circuit the cornerstone for new telecommunication switching products     

An expandable time-division circuit switching LSI and networkarchitecture for broadband ISDN

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking     

A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6-μm high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm×4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s     

Low loss and high extinction ratio strictly nonblocking 16×16thermooptic matrix switch on 6-in wafer using silica-based planarlightwave circuit technology

We describe a silica-based 16×16 strictly nonblocking thermooptic matrix switch with a low loss and a high extinction ratio. This matrix switch, which employs a double Mach-Zehnder interferometer (MZI) switching unit and a matrix arrangement to reduce the total waveguide length, is fabricated with 0.75% refractive index difference waveguides on a 6-in silicon wafer using silica-based planar lightwave circuit (PLC) technology. We obtained an average insertion loss of 6.6 dB and an average extinction ratio of 53 dB in the worst polarization case. The operating wavelength bandwidth completely covers the gain band of practical erbium-doped fiber amplifiers (EDFAs). The total power consumption needed for operation is reduced to 17 W by employing a phase-trimming technique which eliminates the phase-error in the interferometer switching unit     

Implementation of a 16 to 16 switching element for ATM exchanges

The authors describe the implementation of an asynchronous transfer mode (ATM) switching element with 16 inlets and 16 outlets at 600 Mb/s each. The single board switching element is used as a basic switching block in a connection-oriented ATM switching network. The design of the switching element was carried out by using advanced BiCMOS technologies. It is shown how the functional scheme is translated into a feasible chip partitioning and which design options were taken. In particular, the design of the cell switching facility and the queueing memory is treated in detail. A comparison between memory pooling or individual output queues is presented. By making the choice of the latter solution, the development schedule could be kept very tight. Second, the testability of the chips remains good despite the high gate complexity     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

ATM in B-ISDN communication systems and VLSI realization

The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-μm VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology     

A scalable ATM switching system architecture

The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers     

A photonic front-end processor in a WDM ATM multicast switch

Dense wavelength-division multiplexing (DWDM) technology has provided tremendous transmission capacity in optical fiber communications. However, switching and routing capacity is still far behind transmission capacity. This is because most of today's packet switches and routers are implemented using electronic technologies. Optical packet switches are the potential candidate to boost switching capacity to be comparable with transmission capacity. In this paper, we present a photonic asynchronous transfer mode (ATM) front-end processor that has been implemented and is to be used in an optically transparent WDM ATM multicast (3M) switch. We have successfully demonstrate the front-end processor in two different experiments. One performs cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5 Gb/s. The other performs cell synchronization, where cells from different input ports running at 2.5 Gb/s are phase-aligned in the optical domain before they are routed in the switch fabric. The resolution of alignment is achieved to the extent of 100 ps (or 1/4 bit). An integrated 1×2 Y-junction semiconductor optical amplifier (SOA) switch has been developed to facilitate the cell synchronizer     

A prototype broadcast-and-select photonic ATM switch with a WDMoutput buffer

A rack-mounted prototype of a broadcast-and-select (B and S) photonic ATM switch is fabricated. This switch has an optical output buffer utilizing wavelength division multiplexed (WDM) signals. The WDM technology solves. The cell-collision problem in a broadcast-and-select network and leads to a simple network architecture and the broadcast/multicast function. The prototype can handle 10-Gb/s nonreturn-to-zero (NRZ) coded cells and 5-Gb/s Manchester-coded cells and has a switch size of four. In this prototype, the level and timing design are key issues. Cell-by-cell level fluctuation is overcome by minimizing the loss difference between the optical paths and adopting a differential receiver capable of auto-thresholding. The temperature control of delay lines was successful in maintaining the phase synchronization. Using these techniques, we are able to provide a WDM highway with a bit error rate of less than 10^-12. Fundamental photonic ATM switching functions, such as optical buffering and fast wavelength-channel selection, are achieved. We show our experimental results and demonstrate the high performance and stable operation of a photonic ATM switch for use in high-speed optical switching systems as an interconnect switch for a modular ATM switch and an ATM cross-connect switch     

TORUS: terabit-per-second ATM switching system architecture basedon distributed internal speed-up ATM switch

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4×2 switch module using optical interconnection technology and very high-speed crosspoint LSIs, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch     

Low power optical gate HBT driver array for 2.5 Gbit/s ATMswitching

A four element driver array for optical gates in a 2.5 Gbit/s optical ATM switch is presented. The circuit uses a GaAs-GaAlAs heterojunction bipolar transistor (HBT) technology. It enables a switching time of <300 ps and current up to 150 mA with <400 mW per gate power consumption     

A 2 Gb/s expandable space-division switching LSI and networkarchitecture for gigabit-rate broad-band circuit switching

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16×16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated     

Design of a CMOS buffered switch for a Gigabit ATM switchingnetwork

This paper presents the implementation and design of a gigabit ATM Switch element used in a broadcast ATM switching network supporting 600 Mb/s link rates. The system is designed to operate at the clock speed of 100 MHz. The design of the switch element is developed to fabricate prototype chips using 1.2 μ CMOS VLSI technology. The network is constructed with a 256-port Benes topology and the switch element consists of nine identical data slices, and a global controller. Each data slice uses 48 shared buffers. The controller determines which buffer cells are to be sent to the outputs based on its internal contention resolution process. This process is carried out by an arbitration circuit and the decision is made by a buffer control circuit. The controller also generates grant flow control through the network     

Physical performance limits for shared buffer ATM switches

Performance studies, linking ATM switch capabilities to physical limitations imposed by integrated circuit technology, have been scarce. This paper explores trends in circuit capabilities, and makes projections toward the 0.25-μm technologies that will be available to all switch designers in the year 2000. The limits imposed by circuit technology are applied to shared buffer ATM switches. We determine requirements and physical limits for buffer capacity, buffer throughput, chip I/O throughput, and power dissipation. As a result, we are able to project chip counts, aggregate switch throughputs, and switch dimensions. As well, performance capabilities of single-chip shared buffer switches are estimated. A single-chip shared buffer switch implemented in 0.25-μm technology will be capable of an aggregate throughput of 1.3 Tb/s, will accomplish almost arbitrarily low cell loss rates for bursty traffic, and may be integrated together with translation tables supporting hundreds of connections per port     

Monolithically Integrated InP 1 $times$ 16 Optical Switch With Wavelength-Insensitive Operation

The static and dynamic characteristics of a monolithically integrated InP 1$,times,$ 16 optical phased-array switch are presented. The device demonstrates static switching with an average extinction ratio of 18.6 dB, on-chip loss below 7 dB, and wavelength dependence of less than 0.8 dB in the entire $C$-band. A 40-Gb/s nonreturn-to-zero signal is transmitted through the switch with a power penalty below 0.4 dB. Using a programmable electronic circuit, dynamic switching to all 16 outputs is achieved with response times less than 11 ns.      

Low-loss and high-extinction-ratio silica-based strictlynonblocking 16×16 thermooptic matrix switch

A low-loss and high-extinction-ratio silica-based 16×16 thermooptic matrix switch is demonstrated. The switch, which employs a double Mach-Zehnder interferometer switching unit and a matrix arrangement which reduces the total waveguide length, is fabricated with 0.75% refractive index difference waveguides on a 6-in silicon wafer. The average insertion loss and the average extinction ratio are 6.6 and 55 dB, respectively. The total power consumption is 17 W     

Scalable multi-QoS IP+ATM switch router architecture

This article proposes a scalable multi-QoS IP+ATM switch router architecture. The proposed switch router is based on a core ATM switching system with multi-QoS capability. Forwarding engines and a routing engine are attached in front of the line cards of the ATM switching system. The FEs and RE are interconnected with each other via internal VCs. A novel longest matching algorithm is employed at the FE to achieve packet forwarding at wire-speed of OC-12c rate (622.08 Mb/s). Wire-speed unicast and multicast packet forwarding are performed using point-to-point and point-to-multipoint VCs in a unified way. Because FEs and RE are decoupled from the base ATM switching system, the full spectrum of ATM QoS capability is nicely applied for IP QoS control with a packet classification at the edge of the network. The core switching fabric is scalable from 40 to 160 Gb/s capacity (371 MPPS in terms of packet forwarding throughput). Feedback rate control is employed at each line card to eliminate congestion in the high-speed core switching fabric even with a small amount of buffer.