一种光通信同步电路的设计

介绍了一种光纤通信系统中基于FPGA的同步电路的原理,该电路实现了同步电路的全数字化.在MAX PLUS Ⅱ仿真环境下结合原理图和VHDL语言实现了位同步和帧同步电路的综合、仿真和配置.仿真结果表明,该电路能比较准确地恢复位同步和帧同步信号,性能优于传统的集成电路,具有较高的使用价值.     

一种基于FPGA帧同步电路设计

描述了一种基于FPGA实现的数字通信系统帧同步电路原理，在MAX＋PLUSII平台上采用图形设计和VHDL硬件描述语言设计方式设计了数字通信系统帧同步电路，详细说明了关键部分的设计过程，给出了设计的项层文件和相关的仿真图，整个电路可集成到FPGA芯片中，是实现通信系统的全数字化的基础。     

基于混沌同步的混沌脉冲定位调制研究

随着混沌理论和混沌同步的发展及完善，根据混沌脉冲定位调制（CPPM）的基本原理，提出一种基于混沌同步的混沌脉冲定位调制（CS—CPPM）实现方法，建立以蔡氏混沌同步电路和Logstic映射为例的实现模型，用EWB仿真软件对蔡氏二极管、蔡氏电路以及蔡氏同步电路进行分析和实现，最后用Matlab对整个系统进行仿真，实验结果论证了该方法的可行性．这样使得混沌脉冲定位调制信号可以利用现有的混沌映射实现．从而具有多样性和稳定的混沌特性。也使得混沌脉冲定位调制（CPPM）技术具有更多的实现途径和更深的研究与应用价值。     

蔡氏电路混沌同步保密通讯

两个相同的蔡氏电路(Chua’s Circuit)互相耦合可以实现混沌(Chaos)同步是混沌研究的一个重要成果．也是探索蔡氏电路开发应用的基础。应用蔡氏电路的同步特性实现保密通讯是当前蔡氏电路开发应用研究的一个主要方向。本文在介绍蔡氏电路混沌同步特性的基础上，讨论主—从式蔡氏电路同步保密通讯系统及实现双向通讯和无线传输的可行性．并对这种保密通讯系统的安全性与鲁棒性(Robustness)作了简要的分析.     

基于同步状态机的帧同步实现

采用FPGA设计了一种基于同步状态机的帧同步检测电路，具有帧同步的前方保护和后方保护以及接收端的定时功能。全部电路由硬件描述语言实现。可以集成在一片CPLD或FPGA芯片内部，用于数字通信系统接收端的帧同步和定时。     

一种光纤通信系统中帧同步电路的设计

描述了一种光纤通信系统中基于FPGA实现的全数字通信系统同步电路的原理.在MAX PLUSⅡ环境下结合原理图和VHDL语言进行了综合、仿真和配置,该电路实现了同步电路的全数字化.测试结果表明,该设计方法能比较准确地恢复同步信号.     

耦合受迫RC振子之间的混沌同步

混沌同步因其深远的应用潜力受广泛关注，本文首先介绍能产生混沌态的受迫RC振子电路，及由两个这样的电路线性耦合组成的耦合RC振子电路；然后对该耦合电路的动力学过程进行了分析描述，阐明了耦合系统的同步稳定性；数值实验表明，两个电路参数完全相同或两个电路参数略有差异，耦合系统均能实现同步，最后进行了简要讨论。     

数字数据网的原理

数字数据网的原理李朝举１．原理和组成数字数据网（ＤＤＮ）基于同步时分复用、电路交换的基本原理实现。ＤＤＮ只有交叉连接、提供专用电路的功能，因此，不需要信令、不需要用户编号。ＤＤＮ要求网络同步，可采用等级同步和／或准同步方式实现。ＤＤＮ节点都要和网管设...     

基于Chua电路混沌同步自保持特性的研究

本文介绍了Chua电路及其特性，给出实现非线性电阻的一种电路；利用Chua电路构造出一种驱动-响应混沌同步系统，利用仿真得出此同步系统具有一定鲁捧性，抗干扰等特性；根据此同步系统，仿真发现混沌同步具有自保持特性，并给出仿真结果，这一发现为混沌在保密通信的实际应用提供了依据．     

基于FPGA的锁相环敛同步提取电路设计

本文介绍了一种锁相环位同步提取电路的组成和工作原理，并用FPGA实现了该电路，给出了实测的波形。     

IC signal-processing circuit for TV receivers

An IC signal-processing circuit that can be applied in both black-and-white and color receivers is described. The integrated circuit combines the following functions: video preamplifier; keyed AGC detector, operating on top sync level; AGC amplifier for IF and tuner control; noise canceling circuits for AGC and sync circuits; sync separator; automatic horizontal sync; and vertical sync pulse separator. Due to the noise-canceling circuit a stable synchronization is obtained when impulse noise is received. Since the values of the capacitors in the AGC circuit can be rather low without difficulties with instabilities, the performance during fast input signal fluctuations (airplane flutter) is very good.     

A Quick-Look Decoder with Isolated Error Correction and Node Synchronization

In a low-noise environment, a simple inversion circuit can be used for quick-look decoding of a convolutional code. The bit error performance of the raw inversion circuit is improved by a simple pattern-recognition technique operating on the syndrome stream, which is also used to acquire node sync.     

DAB接收机RF模块灵敏度与同步速度优化方法的研究

对DAB接收机灵敏度与同步速度的电路优化主要通过对RF模块外围电路的优化来实现。在研究DAB接收机RF模块的中频反馈电路和DAB信号同步控制原理的基础上,研究了反馈电路的优化方法,分析了同步慢的原因,提出了解决方案。测试记录表明：增加一条快速泄放电路可改善同步速度,提高反馈电压增加下信号的增长率益。     

距离选通水下激光成像系统设计及实验

针对浅水目标探测这一难题,设计了一种基于距离选通技术的水下成像系统。系统围绕532nm Nd…YAG脉冲激光器和选通式增强型电荷耦合器件(ICCD)摄像机搭建而成,并且采用激光脉冲作为系统同步控制的触发信号。采用基于现场可编程门阵列(FPGA)技术设计的同步控制电路,进行了距离选通水下激光成像实验。实验结果表明,采用激光脉冲触发同步控制电路的方法,可有效抑制激光脉冲抖动对系统同步控制精度的影响,从而克服水体表面反射和后向散射对成像的影响,提高了成像质量。在有效衰减系数为0.52m-1的湖泊中,系统的成像深度可达到水下7m,对于浅水目标的探测、识别非常有效。     

Experimental sync separator and associated circuitry in integrated form

An experimental integrated circuit that performs the functions of sync separation, noise inversion, and AGC amplification was designed and fabricated. The IC uses p-channel enhancement-type MOS units as active transistors, diodes, and resistors. The threshold voltages permit the design of voltage-regulator circuits for the reference levels in the various signal-processing stages. The results of a test of the IC in combination with a commercial TV receiver are described.     

高功率微波发射机调制器和电源电路设计

为使高功率发射机的行波管正常工作,设计了其调制器和电源电路.用双稳态触发电路和脉冲变压器组合构成了调制器电路,输出上升沿和下降沿陡峭、时间关系与同步触发脉冲一致的调制脉冲,加到行波管的控制栅极;采用串联型开关电源电路,产生了行波管正常工作所需的低压电源;利用脉冲变换器和高压变压器产生了行波管的高压电源;此外还设计了控制...     

Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors

Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1-1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features ~37% lower energy per FFT/IFFT computation than the sync approach but with ~10% larger IC area penalty and an inconsequential 1.4 times worse delay; the async design can be designed to be 0.24 times faster and with largely the same energy dissipation if the matched delay elements and the latch controllers therein are better optimized. In this low-speed application, the lower energy feature of the async design is not attributed to the absence of the clock infrastructure but instead due to the adoption of established and proposed async circuit designs, resulting in reduced redundant operations and reduced spurious/glitch switching, and to the use of latches. The prototype async FFT/IFFT processor (in a 0.35-mum CMOS process) can be operated at 1.0 V and dissipates 93 nJ.     

基于74LS160的N进制计数器仿真设计

针对任意进制（N进制）计数器的设计目的,采用反馈复零法对基于同步十进制计数器74LS160进行设计,分别采用异步清零法实现了6进制计数器和同步置数法实现7进制计数器的设计,通过应用EWB软件对所设计的电路进行仿真实验,仿真结果表明设计的计数器能实现所要求的N进制技术功能.最终得出采用反馈复零法可以实现进制计数器的结论.     

计算机彩色显示器信号源

在维修CRT式节能型计算机彩色显示器时,若采用专用的计算机显示器信号源能避免因显示器的频繁开关而损坏主机显卡,操作需要时可直接开关显示器,无需考虑信号源的安全,大大方便维修操作。由7555时基IC构成的振荡器、触发器与用CD4060二进制串行计数器、74LS161二进制同步计数器等构成的分频电路能够组成满足上述要求的计算机彩色显示器信号源。     

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.