数控直流稳压电源设计

常规线性稳压电源中,调整元件串联在负载回路,其作用就像一只可变电阻,输入电压或负载变化时,串联调整元件的压降改变,从而使输出电压稳定不变。当输入电压过高时,串联调整管的功耗很大,因此效率很低。为了解决常规线性电源采用滑动电阻调节方式所带来的低效率问题,通过采用数字控制的方法,使线性电源的效率最大化。该设计利用STC12C5410AD单片机输出PWM控制三端稳压器,实际带载测试在输入电压波动范围为±20%的情况下,效率达到了50%的结果,证明数控型电源具有工作稳定,电压调节精度高,纹波系数小,效率高于常规线性电源的特点。     

A New Analog Controller for Three-Phase Four-Wire Voltage Generation Inverters

This paper introduces a new controller for three-phase four-wire inverters, with the control goal of generating high-quality three-phase output voltages for all sorts of linear/nonlinear and balanced/unbalanced loads. The proposed controller employs a circuit-level decoupling method, and it is implemented by logic circuitry in combination with a control core and a feedback signal processor. Almost all dc–dc control methods can be adapted as the control core, while the feedback signal processor can be implemented by either voltage compensator and/or current compensator. The implementation of the controller is simple and flexible with only logic and analog circuitry needed. Yet, it demonstrated experimentally excellent load handling and source voltage noise rejection ability. The prototype is tested under balanced and unbalanced resistive and nonlinear loads, as well as under extreme load transients. It is also tested with power from a noisy dc input source. In all cases, the prototype demonstrated high-quality output voltages.      

Control of distributed generation systems-Part I: Voltages and currents control

This paper discusses a digital control strategy for three-phase pulse-width modulation voltage inverters used in a single stand-alone ac distributed generation system. The proposed control strategy utilizes the perfect robust servomechanism problem control theory to allow elimination of specified unwanted voltage harmonics from the output voltages under severe nonlinear load and to achieve fast recovery performance on load transient. This technique is combined with a discrete sliding mode current controller that provides fast current limiting capability necessary under overload or short circuit conditions. The proposed control strategy has been implemented on a digital signal processor system and experimentally tested on an 80-kVA prototype unit. The results showed the effectiveness of the proposed control algorithm.     

A 90-nm variable frequency clock system for a power-managed itanium architecture processor

An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a power management scheme which maximizes processor performance within a configured power envelope. Core supply voltage and clock frequency are modulated dynamically in order to remain within the power envelope. The Foxton controller and dynamically-variable clock system reside on die while the variable voltage regulator and power measurement resistors reside off chip. In addition, high-bandwidth frequency adjustment allows the clock period to adapt during on-die supply transients, allowing higher frequency processor operation during transients than possible with a single-frequency clock system.     

数字控制通讯电源高压防护研究

介绍了一种数字控制通讯电源高压防护电路及其控制方法。数字信号控制器通过检测交流输入电压和PFC输出电压状况做出智能判断,控制高压防护电路中主继电器和辅助继电器的断开和吸合状态,从而对实现通讯电源快速有效的高压防护,提高了通信电源的可靠性。     

A New Analog Controller for Three-Phase Voltage Generation Inverter

This paper introduces a new controller for a threephase inverter, with a control goal of generating desired threephase output voltages. The proposed controller employs a circuit-level decoupling method, and it is implemented by logic circuitry in combination with a control core and a feedback signal processor. Almost all DC-DC controllers can be adapted as the control core, whereas the feedback signal processor can be implemented by either voltage compensator and/or current compensator. The controller's implementation is simple and flexible with logic and analog circuitry. Yet, it demonstrates experimentally excellent load handling, source voltage noise rejection, and reference tracking ability. The prototype is tested under resistive load, highly nonlinear load, and extreme load transients; aside from that, it is also tested under noisy source voltage and sudden reference change. In all cases, the prototype demonstrated high-quality output voltages.     

Digital control of a voltage-mode synchronous buck converter

A digital control algorithm capable of separately specifying the desired output voltage and transient response for a synchronous buck converter operating in voltage mode was developed. This algorithm is based on superimposing a small control signal onto a voltage reference at each switching cycle to cancel out the perturbations. A zero steady-state error in the output voltage can be obtained with the aid of additional dynamics to allow the controller to track a load change and update the reference to a new load state. The specifications of the control algorithm are achieved by pole placement using complete state feedback. The control algorithm was implemented on a digital signal processor (DSP)-controlled synchronous buck converter.     

Predictive digital control of power factor preregulators with input voltage estimation using disturbance observers

The paper presents a fully digital control of single-phase boost power factor preregulators (PFPs) based on inductor (or switch) current and output voltage measurements. Input voltage sensing is avoided using a disturbance observer, which provides a waveform proportional to the rectified input voltage. The proposed solution is based on a multiloop structure for PFPs with an internal deadbeat current control and a conventional outer voltage control, possibly with fast dynamic response. The resulting control algorithm is simple, accurate, and robust with respect to parameter mismatch. The digital control has been implemented both in a field programmable gate array and in a digital signal processor (TMS320F2812), to test the proposed algorithm with different control delays. Experimental results on a single-phase boost PFPs show the effectiveness of the proposed solution.     

An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction

An integrated adaptive-output switching converter is presented. This converter adopts one-cycle control for fast line response and dual error correction loops for tight load regulation. A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process. The design accommodates both continuous and discontinuous conduction operations. To further enhance the efficiency, dynamic loss control on the power transistors is proposed to minimize the sum of switching and conduction losses. The design can be extended to other dc-dc and ac-dc conversions. The prototype of the buck converter was fabricated with a standard 0.5-/spl mu/m digital CMOS process. Experimental results show that the converter is well regulated over an output range of 0.9-2.5 V, with a supply voltage of 3.3 V. The tracking speeds are 12.25 /spl mu/s/V for a 1.6-V step-up output change and 13.75 /spl mu/s/V for a 1.6-V step-down output change, respectively, which are much faster than existing counterparts. Maximum efficiency of 93.7% is achieved and high efficiency above 75% is retained over an output power ranging from 10 to 450 mW.     

Single-stage three-phase buck-boost type AC-DC converter with highpower factor

A new control process for single-stage three-phase buck-boost type AC-DC power converters with high power factor, sinusoidal input currents and adjustable output voltage is proposed. This converter allows variable power factor operation, but this work focus on achieving unity power factor. The proposed control method includes a fast and robust input current controller based on a vectorial sliding mode approach. The active nonlinear control strategy applied to this power converter, allows high quality input currents. Given the comparatively slow dynamics of the DC output voltage, a proportional integral (PI) controller is adopted to regulate the converter output voltage. The voltage controller modulates the amplitudes of the current references, which are sinusoidal and synchronous with the input source voltages. Experimental results from a laboratory prototype show the high power factor and the low harmonic distortion characteristics of the circuit     

A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems

This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2⁴ FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FFT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 times1.88 mm² . The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.     

An audio amplifier providing up to 1 Watt in standard digital 90-nm CMOS

An audio amplifier in a standard 90-nm dual gate-oxide CMOS technology is designed for direct connection to the battery in a mobile phone. Special techniques have been applied to run it from a supply voltage of up to 5.5 V. The circuit does not require a dedicated supply voltage generator; it can be integrated on the same chip with the digital signal processor, and provides high output power, good power supply rejection, and good efficiency.     

A novel high-performance voltage regulator for single-phase ACsources

Regulation of load voltage in single-phase applications is becoming an important issue for critical loads. This paper presents a novel high-performance single-phase voltage regulator which has a common arm between the rectifier and inverter, and adopts an appropriate switching strategy. The proposed voltage regulator employs six switches and can be implemented by only one three-phase inverter module. The proposed voltage regulator has the capability of delivering sinusoidal input current with unity power factor, good output voltage regulation, and bidirectional power flow. For these purposes, a fully digital controller is designed and implemented using a TMS320F240 digital signal processor. In addition, a novel low-cost AC capacitor is also presented. This type of capacitor requires two DC capacitors and two diodes, enabling low-cost and compact manufacturing. Consequently, the complete voltage regulator system, which is mainly suitable for an uninterruptible power supply as well as reactive or nonlinear loads, can be constructed compactly and inexpensively. Experimental results are presented to verify the feasibility of the proposed voltage regulator system     

Direct repetitive control of SPWM inverter for UPS purpose

A novel repetitive controller directly combined with an open loop SPWM inverter is presented in this paper. To cope with the high-resonant peak of the open loop inverter that may cause instability, a zero-phase-shift notch filter other than the inverse transfer function of the inverter or a conventional second-order filter is incorporated in the controller. The proposed method has good harmonic rejection and large tolerance to parameter variations. To further reduce the steady-state error, a low-pass-filter Q(z) algorithm is applied. The DC bias problem is also taken into consideration and solved with the repetitive controller itself. The method is implemented with a digital signal processor and achieves low THD% (1.4%-1.7%) with nonlinear loads and fast error convergence (3-5 fundamental periods). It proves to be a cost-effective solution for common UPS products where high-quality output voltage is more stressed than fast dynamic response.     

A reconfigurable analog processor using coarse-grained,heterogeneous configurable analog blocks for field programmable mixed-signal processing

A field programmable analog array (FPAA), designed for a reconfigurable analog processor, introduces coarse-grained, heterogeneous configurable analog blocks that improves performance and power consumption. Designed in an SMIC standard 0.18 μm CMOS process, mixed-signal processing can be performed by the assistance of an on-chip MCU and configurable digital blocks. Relative precision of the analog processing is 99.5%. A PID controller is shown as an application example. With a total die area of 11 mm², the maximum power consumption is 17.6 mA with a 3.3 V supply voltage, resulting in a 17× improvement in energy-efficiency over current conventional FPAAs.     

电参量测试仪的系统设计

介绍了谐波功率测量的数字信号处理算法以及一种基于DSP技术的多功能电参量测量仪的系统设计。采用DSP和MPU及A/D等集成电路构成系统实现了电流和电压的平均值、有功功率及功率因数等电力参数的测量及波形显示。本系统还可以通过通信模块进行远程测量和数据传输。     

基于TMS320F28335的永磁同步电动机控制器的设计

针对永磁同步电机（PMSM）具有结构简单、效率高、功率因数高等优点,研究和设计了一款以浮点型TMS320F28335数字信号处理器（DSP）为控制核心的永磁同步电机控制器。该控制器设计了三相全控桥式功率驱动电路和过流、欠压检测,温度监控等检测保护电路。能通过CAN总线连接外部显示模块以及RS232通信接口与上位机的高速通信并进行实时数据交换,软件部分采用空间矢量算法实现电流、速度和位置的精确控制。实验结果表明,控制器精度高、响应快、控制效果稳定。     

High-power-factor electronic ballast with constant DC-link voltage

This paper presents a high-power-factor (HPF) electronic ballast based on a single power processing stage with constant DC-link voltage. The switching frequency is controlled to maintain the DC-link voltage and the voltage across the switches constant, independently of changes in the AC-input voltage. This control method assures zero-voltage switching (ZVS) for the specified AC-input-voltage range. Besides, with an appropriate design of the fluorescent lamps' drive circuit, the lamps' power can be kept close to the rated value. The power-factor-correction (PFC) stage is formed by a boost power converter operating in the discontinuous conduction mode, which naturally provides HPF to the utility line. The fluorescent lamps are driven by an unmodulated sine-wave current generated from an LC parallel resonant power converter which operates above the resonant frequency to perform ZVS. Theoretical analysis and experimental results are presented for two series-connected 40 W fluorescent lamps operating from 127 V -15% to +10% 60 Hz utility line. The switching frequency is changed from 25 to 45 kHz to maintain the DC-link voltage regulated at 410 V, which leads to a constant output power. The experimental results confirm the high efficiency and HPF of this electronic ballast     

A rail-to-rail, constant gain, buffered op-amp for real time videoapplications

Inspired by Hogervorst et al's current switch idea, a buffered output stage operational amplifier was designed, which has high frequency, high dc gain, and rail-to-rail constant transconductance (G _m). This operational amplifier is the output stage of an analog/digital system which implements a Gabor convolution for real-time dynamic image processing and it is designed to interface the external analog-to-digital converter (ADC) with a very heavy load. The op amp was fabricated by the MOSIS service in a 2-μm, n-well CMOS, double polysilicon, double metal technology. The fabricated circuit operates from a single 5 V power supply and dissipates 10 mW. The open loop-gain of the fabricated circuit, A_vol, was measured as 67.2 dB for a 163 Ω∥33 pF load. Other dc and ac characteristics were measured for a 50 Ω∥33 pF load. The unify gain-bandwidth (GBW) was measured to be 11.4 MHz, the rising slew rate (SR+) 20.4 V/μs, the falling slew rate (SR-) 18.8 V/μs, and the offset voltage (V_off) 1 mV. The output swings with an amplitude of 3.24 V between 0.88 V and 4.12 V, which matches the input signal specifications of the ADC. In addition to rail-to-rail output voltage swing, the opamp has a constant G_m over the whole common mode (CM) voltage range