倒装芯片键合技术发展现状与展望

我国集成电路发展十二五规划中提到,大力发展先进封装和测试技术,推进高密度堆叠型三维封装产品的进程,支持封装工艺技术升级和产能扩充。阐述了先进封装技术中的倒装芯片键合工艺现状及发展趋势,以及国际主流倒装设备发展及国内应用现状,重点介绍了北京中电科装备有限公司的倒装机产品。国产电子装备厂商应认清回流焊倒装芯片键合设备市场发展,缩短倒装设备产品开发周期和推向市场的时间,奠定国产电子先进封装设备产业化基础;同时抓紧研发细间距铜柱凸点倒装和热压焊接技术,迎接热压倒装芯片工艺及其设备的挑战。     

用于倒装芯片的晶片凸点制作工艺研究

倒装芯片在电子封装互连中占有越来越多的份额,是一种必然的发展趋势,所以对倒装芯片技术的研究变得非常重要。倒装芯片凸点的形成是其工艺过程的关键。现有的凸点制作方法主要有蒸镀焊料凸点、电镀凸点、微球装配方法、焊料转送、在没有UBM的铅焊盘上做金球凸点、使用金做晶片上的凸点、使用镍一金做晶片的凸点等。每种方法都各有其优缺点,适用于不同的工艺要求。介绍了芯片倒装焊基本的焊球类型、制作方法及各自的特点,总结了凸点制作应注意的问题。     

微波芯片倒装金凸点热疲劳可靠性分析及优化

为了满足射频系统小型化的需求,提出了一种基于硅基板的微波芯片倒装封装结构,解决了微波芯片倒装背金接地的问题.使用球栅阵列(BGA)封装分布为周边型排列的GaAs微波芯片建立了三维有限元封装模型,研究了微波芯片倒装封装结构在-55～125℃热循环加载下金凸点上的等效总应变分布规律,同时研究了封装尺寸因素对于金凸点可靠性的影响.通过正交试验设计,研究了凸点高度、凸点直径以及焊料片厚度对凸点可靠性的影响程度.结果表明:金凸点离芯片中心越近,其可靠性越差.上述各结构尺寸因素对凸点可靠性影响程度的主次顺序为:焊料片厚度＞金凸点直径＞金凸点高度.因此,在进行微波芯片倒装封装结构设计时,应尽可能选择较薄的共晶焊料片来保证金凸点的热疲劳可靠性.     

芯片级封装技术研究

对刚性基板倒装式和晶圆再分布式两种结构的芯片级封装（CSP）进行了研究，描述了CSP的工艺流程；详细讨论了CSP的几项主要关键技术：结构设计技术，凸点制作技术，包封技术和测试技术；阐述了采用电镀和丝网漏印制备焊料凸点的方法。     

采用热压焊工艺实现金凸点芯片的倒装焊接

金凸点芯片的倒装焊接是一种先进的封装技术.叙述了钉头金凸点硅芯片在高密度薄膜陶瓷基板上的热压倒装焊接工艺方法,通过设定焊接参数达到所期望的最大剪切力,分析研究互连焊点的电性能和焊接缺陷,实现了热压倒装焊工艺的优化.同时,还简要介绍了芯片钉头金凸点的制作工艺.     

满足互连要求的无铅化工艺和材料

在走向无铅化的道路上，为了能够满足倒装芯片和晶圆级封装、SMT以及波峰焊接的需要，要求对各种各样的材料和工艺方案进行研究。为了能够满足电路板上的倒装芯片和芯片规模封装技术，需要采用合适的工艺技术和材料。采用模板印刷和电镀晶圆凸点工艺，可以实现这一目标。     

适合于印刷工艺的IndiumTacflux676助焊剂在倒装芯片装配过程中的应用

倒装芯片是一种无弓1脚结构的芯片互联技术,它起源于60年代,由IBM率先研发,具体原理是在I／O板上沉积焊料凸点,然后将芯片翻转加热利用熔融的焊料凸点与基板相结合,此技术代替了常规的打线接合,在封装技术的应用范围日益广泛,己逐步成为高端器件及高密度封装领域中经常采用的封装形式,特别是它可以采用类似SMT技术（印刷）的手段来加工生产效率将有大幅的提升,因此倒装芯片封装技术将是高密度芯片封装的最终方向。     

一种新型的BBUL封装技术

无凸点叠层封装（BBUL）技术是Intel公司研制出的一种新型封装技术，用以满足未来微处理器封装技术的要求。这种BBUL封装技术具有很大的优越性，它免除了大多数高性能的倒装芯片所用的大量焊料凸点和互连，使环路电感量小、热机械应力小，不但减小芯片连接的寄生效应，而且提高了微处理器芯片的效率。此外，该封装的体积比传统封装更小、更轻，使多芯片之间的互连更为紧密。特别适合于高引出端的电子类及光电子产品，如逻辑单元、存储器、射频器件以及微型机电一体化系统。本文主要从其发展背景、工艺及特性方面，来阐述这种新型的BBUL封装技术，最后提出一些建议。     

一种新型的BBUL封装技术

无凸点叠层封装（BBUL）技术是Intel公司研制出的一种新型封装技术，用以满足未来微处理器封装技术的要求。这种BBUL封装技术具有巨大的优越性，它免除了大多数高性能的倒装芯片所用的大量焊料凸点和互连，使环路电感量小、热机械应力小，不但减小芯片连接的寄生效应，而且提高了微处理器芯片的效率。此外，该封装比传统封装更小、更轻，使多芯片之间的互连更为紧密，特别适合于高引出端的电子类及光电子产品，如逻辑单元、存储器、射频器件以及微型机电一体化系统。本文主要从其发展背景、工艺及特性方面来阐述这种新型的BBUL封装技术，最后提出一些建议。     

热-电耦合下倒装芯片封装焊点的电迁移失效研究

热电交互作用下产生的电迁移现象成为倒装芯片封装关键的可靠性问题。建立了FCBGA(倒装芯片球栅陈列封装)三维封装模型,研究了热-电交互作用下倒装芯片互连结构中的温度分布、电流密度分布以及焦耳热分布;发现焊料凸点中存在严重的焦耳热和电流聚集现象;分析了焊料凸点中热点出现的原因,并发现热点在焊料凸点空洞形成过程中起到了关键作用。     

Effect of bump height on the strain variation during the thermalcycling test of ACA flip-chip joints

Flip chip joining using anisotropically conductive adhesive (ACA) has become a very attractive technique for electronics packaging. Many factors can influence the reliability of the ACA flip-chip joint. Bump height, is one of these factors. In this work, the strain development during the thermal cycling test of flip-chip joining with different bump heights was studied. The effect of bump height is significant in the interface between the bumps and the pads. Bigger volume area of high strain is found for higher bump in the interface between the bumps and the pads. Our calculations show that there is practically no effect of the bump height on the strain variation in the bumps and in the pads     

Defect inspection of solder bumps using the scanning acoustic microscopy and fuzzy SVM algorithm

Flip chip technology has been extensively used in high density electronic packaging over the past decades. With the decrease of solder bumps in dimension and pitch, defect inspection of solder bumps becomes more and more challenging. In this paper, an intelligent diagnosis system using the scanning acoustic microscopy (SAM) is investigated, and the fuzzy support vector machine (F-SVM) algorithm is developed for solder bump recognition. In the F-SVM algorithm, we apply a fuzzy membership to input feature data so that the different input features can make different contributions to the learning procedure of the network. It solves the problem of feature data aliasing in the traditional SVM. The SAM image of flip chip is captured by using an ultrasonic transducer of 230 MHz. Then the segmentation of solder bumps is based on the gradient matrix of the original image, and the statistical features corresponding to every solder bump are extracted and adopted to the F-SVM network for solder bump classification and recognition. The experiment results show a high accuracy of solder defect recognition, therefore, the diagnosis system using the F-SVM algorithm is effective and feasible for solder bump defect inspection.     

倒装晶片(Flip Chip)装配工艺及其对表面贴装设备的要求

元件的小型化高密度封装形式越来越多,如多模块封装(MCM),系统封装(SiP),倒装晶片(FC)等应用得越来越多。这些技术的出现更加模糊了一级封装与二级装配之间的界线,勿庸置否,随着小型化高密度封装的出现,对高速与高精度装配的要求变得更加关键。相关的组装设备和工艺也更具先进性与高灵活性。由于倒装晶片比BGA或CSP具有更小的外形尺寸,更小的球径和球间距,它对植球工艺,基板技术,材料的兼容性,制造工艺以及检查设备和方法提出了前所未有的挑战。     

倒装片封装与芯片规模封装的综合比较及其发展前景

本文主要论述了现代微电子封装技术中倒装片封装技术和芯片规模封装技术的结构类型,应用产品,倒装片与晶片级规模封装,并阐述了倒装片封装与芯片规模封装的综合比较及其发展前景。     

BGA／CSP和倒装焊芯片面积阵列封装技术

随着表面安装技术的迅速发展,新的封装技术不断出现,面积阵列封装技术成了现代封装的热门话题,而BGA／CSP和倒装焊芯片（F1iPChip）是面积阵列封装主流类型。BGA／CSP和倒装焊芯片的出现,适应了表面安装技术的需要,解决了高密度、高性能、多功能及高I／O数应用的封装难题。本文介绍了BGA／CSP和倒装焊芯片的封装理论和技术优势及制造流程,并阐述了植球机的基本构成和工作原理。     

面积阵列封装--BGA和Flip Chip

随着表面安装技术的迅速发展,新的封装技术不断出现,面积阵列封装技术成了现代封装的热门话题,ＢＧＡ和ＦｌｉｐＣｈｉｐ是面积阵列封装的两大类型,它们作为当今大规模集成电路的封装形式,引起电子组装界的关注,而且逐渐在不同领域得到应用。ＢＧＡ和ＦｌｉｐＣｈｉｐ的出现,适应了表面安装技术的需要,解决了高密度、高性能、多功能及高Ｉ／Ｏ数应用的封装难题,预计随着进一步的发展,ＢＧＡ和ＦｌｉｐＣｈｉｐ技术将成为     

微电子封装中芯片焊接技术及其设备的发展

概述了微电子封装中引线键合、载带自动键合、倒装芯片焊料焊凸键合、倒装芯片微型焊凸键合等芯片焊接技术及其设备的发展 ,同时报告了世界著名封装设备制造公司芯片焊接设备的现状及发展趋势。     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一.对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素.针对不同清洗方式及参数...     

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects     

Development of gold based solder candidates for flip chip assembly

Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders for interconnecting the chip to a carrier in certain applications due to the unique properties of lead. Despite of all the beneficial attributes of lead, its potential environmental impact when the products are discarded to land fills has resulted in various legislatives to eliminate lead from the electronic products based on its notorious legacy as a major health hazard across the spectrum of human generations and cultures. Flip chip assembly is also now increasingly being used for the high-performance (H-P) systems. These H-P systems perform mission-critical operations and are expected to experience virtually no downtime due to system failures. Thus, reliability of the solder joint is a major critical issue. This reliability is directly influenced by both the phases in the bulk solder and also the intermetallic compounds formed between the solder and the solder wettable layer of the under-bump metallization during both the wetting reaction or/and the solid state ageing. In the present work, an attempt has been made to develop new solder alloys for flip chip assembly using the CALPHAD approach based on gold, the safest element among all the elements being considered for this application. Specifically, efforts have been made to predict the phases in the bulk solder of the promising solder candidates and also the intermetallic compounds formation, using the CALPHAD approach.