通用Toffoli可逆门的固定故障测试

可逆电路技术在低功耗芯片和量子通信中广泛使用。目前,大部分学者着重研究可逆电路的合成,对电路的故障测试却很少问津,但是可逆电路的测试在应用中却十分重要。文中构造了一种四输入通用Toffoli门（universal toffoli gate,UTG）用来检测电路故障,这个门可以实现所有基本的布尔逻辑。UTG门可以检测到所...     

Delay fault propagation in synchronous sequential circuits

Compared with the propagation of logic errors produced by stuck-at faults, the propagation of gate delay fault effects in sequential circuits poses some particular problems. The authors first describe the propagation conditions of such faults then define the propagation rules of these faults which are used in a new delay fault simulation process for synchronous sequential circuits     

Modeling and testing for stuck faults in pseudo nMOS combinational circuits

In this paper, a new transistor model is developed. This model employs the logic transistor function (LTF) to examine the behavior of pseudo nMOS logic circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the following logic values (0, 1, I, M). I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults are analyzed in the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for a specified sub circuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used.     

On the generation of test patterns for multiple faults

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.     

Testability of parity checkers

Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed     

Bilateral Testing of Nano-scale Fault-Tolerant Circuits

As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS’85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.     

Experimental Results for Self-Dual Multi-Output Combinational Circuits

In this short note, the possibilities and the limitations for the application of self-dual circuits with alternating inputs are experimentally investigated. The original circuit is assumed to be given as a netlist of gates. The necessary area overhead, the fault coverage for single stuck-at faults in test mode and the error detection probability in on-line mode due to internal stuck-at faults and stuck-at faults at the input lines are determined for MCNC benchmark circuits.     

Symbolic fault modelling of MOS combinational circuits

This paper presents a new method for fault modelling of MOS combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic value. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as Transistor Logic Conductance Function (TLCF). Starting from a known TLCF, a simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate. Moreover, the method can deal also with bridging and cut faults. Finally, the application of the TLCF for test pattern generation is considered.     

Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors

Switched current (SI) circuits use analogue memory cells as building blocks. In these cells, like in most analogue circuits, there are hard-to-detect faults with conventional test methods. A test approach based on a built-in dynamic current sensor (BIDCS), whose detection method weights the highest frequency components of the dynamic supply current of the circuit under test, makes possible the detection of these faults, taking into account the changes in the slope of the dynamic supply current induced by the fault. A study of the influence of these faults in neighbouring cells helps to minimize the number of BICS needed in SI circuits as is shown in two algorithmic analogue-to-digital converters. Yolanda Lechuga received a degree in Industrial Engineering from the University of Cantabria (Spain) in April 2000. Since then, she has been collaborating with the Microelectronics Engineering Group at the University of Cantabria, in the Electronics Technology, Systems and Automation Engineering Department. Since October 2000 she has been a post-graduate student, to be appointed as lecturer at this university, where she is working in her Ph.D. She is interested in supply current test methods, fault simulation, BIST and design for test of mixed signal integrated circuits. Román Mozuelos received a degree in Physics with electronics from the University of Cantabria, Spain. From 1991 to 1995 he was working on the development of quartz crystal oscillators. Currently, he is a Ph.D. student and an assistant teacher at the University of Cantabria in the Department of Electronics Technology. His interests include mixed-signal design and test, fault simulation, and supply current monitoring. Miguel A. Allende received his graduate degree in 1985 and Ph.D. degree in 1994, both from the University of Cantabria, Santander, Spain. In 1996, he became an Assistant Professor of Electronics Technology at the same Institution, where he is a member of the Microelectronics Engineering Group at the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. His research interests include design of VLSI circuits for industrial applications, test and DfT in digital VLSI communication circuits, and power supply current test of mixed, analogue and digital circuits. Mar Martínez received her graduate degree and Ph.D. from the University of Cantabria (Spain) in 1986 and 1990. She has been Assistant Professor of Electronic Technology at the University of Cantabria (Spain) since 1991. At present, she is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. She has participated in several EU and Spanish National Research Projects. Her main research interest is mixed, analogue and digital circuit testing, using techniques based on supply current monitoring. She is also interested in test and design for test in digital VLSI circuits. Salvador Bracho obtained his graduate degree and Ph.D. from the University of Seville (Spain) in 1967 and 1970. He was appointed Professor of Electronic Technology at the University of Cantabria (Spain) in 1973, where, at present, he is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. He has participated, as leader of the Microelectronics Engineering Group at the University of Cantabria, in more than twenty EU and Spanish National Research Projects. His primary research interest is in the area of test and design for test, such as full scan, partial scan or self-test techniques in digital VLSI communication circuits. He is also interested in mixed-signal, analogue and digital test, using methods based on power supply current monitoring. Another research interest is the design of analogue and digital VLSI circuits for industrial applications. Prof. Bracho is a member of the Institute of Electrical and Electronic Engineers.     

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design, and uses only 2-input AND-OR gates. A universal test set of size (n²/8 + 3n/4) for detecting all single stuck-at faults can be easily determined for an n-input module, where n = 2^k, k ≥ 3. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees full robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those of earlier designs. Results on circuit area and delay for a few benchmark examples are also reported. Hafizur Rahaman received the Bachelor of Electrical Engineering degree from the Bengal Engineering College, Calcutta University, India in 1986, the Master degree in Electrical Engineering, and the Ph.D. degree in computer science and engineering from the Jadavpur University, Calcutta, India in 1988 and 2003 respectively. He is currently chairing the Department of Information Technology, Bengal Engineering and Science University, Shibpur, India. His research interest includes logic synthesis and testing of VLSI circuits, fault-tolerant computing, and quantum computing. He has published several papers in well-known international journals and in reputed conference proceedings. He served in the Organizing Committee of the International Conference on VLSI Design in 2000 and 2005, and as the Registration Chair of the 2005 Asian Test Symposium (ATS), in Kolkata. Debesh K. Das received the Bachelor and Master degrees in electronics and telecommunication engineering, and the Ph.D. degree in computer science and engineering all from the Jadavpur University, Calcutta, India in 1982, 1984, and 1997 respectively. He is currently full professor at the Department of Computer Science and Engineering, Jadavpur University. He visited the University of Potsdam, Germany, the Asian Institute of Technology, Bangkok, the Abdus Salam International Center for Theoretical Physics, Trieste, Italy, and the Nara Institute of Science and Technology, Japan. His research work primarily focuses on logic synthesis and testing of VLSI circuits and fault-tolerant computing. He has published numerous papers in archival journals and refereed international conference proceedings. He served in the Organizing Committee of the International Conference on VLSI Design in 2000 and 2005. He also served as the Organizing Chair of the 2005 Asian Test Symposium (ATS). Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech. degrees in radiophysics and electronics, and the Ph.D. degree in computer science all from the University of Calcutta, India. Since 1982, he has been on the faculty of the Indian Statistical Institute, Calcutta, where currently he is full professor. He held visiting professorship at the University of Nebraska-Lincoln, USA, and at the University of Potsdam, Germany. In 2005, he visited the Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur as VSNL Chair Professor. His research and teaching interest includes logic synthesis, testing and physical design of VLSI circuits, nanotechnology, graph and geometric algorithms, and image processing architecture. He is author of more than 180 papers published in archival journals and refereed conference proceedings, and inventor of 8 United States patents. Currently, he is collaborating with Intel Corporation, USA, and IRISA, France, for development of image processing hardware, chip layout analysis and design, and reconfigurable parallel computing tools. Dr. Bhattacharya is a Fellow of the Indian National Academy of Engineering, a Fellow of the National Academy of Sciences, India, and a recipient of the VASVIK Award for Electronic Sciences and Technology. He is on the editorial board of the Journal of Circuits, Systems, and Computers (World Scientific, Singapore, and the Journal of Electronic Testing—Theory and Applications (Springer).     

Design error diagnosis in digital circuits with stuck-at fault model

In this paper we describe in detail a new method for the single gate-level design error diagnosis in combinational circuits. Distinctive features of the method are hierarchical approach (the localizing procedure starts at the macro level and finishes at the gate level), use of stuck-at fault model (it is mapped into design error domain only in the end), and design error diagnostic procedure that uses only test patterns generated by conventional gate-level stuck-at fault test pattern generators (ATPG). No special diagnostic tests are used because they are much more time consuming. Binary decision diagrams (BDD) are exploited for representing and localizing stuck-at faults on the higher signal path level. On the basis of detected faulty signal paths, suspected stuck-at faults at gate inputs are calculated, and then mapped into suspected design error(s). This method is enhanced compared to our previous work. It is applicable to redundant circuits and allows using incomplete tests for error diagnosis. Experimental data on ISCAS benchmark circuits shows the advantage of the proposed method compared to the known algorithms of design error diagnosis.     

False-Path Removal Using Delay Fault Simulation

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.     

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model.In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.     

Circuit testable design and universal test sets for multiple-valued logic functions

The circuit testable realizations of multiple-valued functions are studied in this letter. First of all, it is shown that one vector detects all skew faults in multiplication modulo circuits or in addition modulo circuits, and n＋1 vectors detect all skew faults in the circuit realization of multiplevalued functions with n inputs. Secondly, min（max） bridging fault test sets with n＋2 vectors are presented for the circuit realizations of multiple-valued logic functions. Finally, a tree structure is used instead of cascade structure to reduce the delay in the circuit realization, it is shown that three vectors are sufficient to detect all single stuck-at faults in the tree structure realization of multiplevalued logic functions.     

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults. Part of this work has ever appeared in the proceedings of Asian Test Symposium in 2003. Yu-Chiun Lin received his BS degrees in Electrical Engineering from National Central University in 2000, and MS degree from Electrical Engineering of National Tsing Hua University in 2002. Since then, he has been with Ali Corporation as a design engineer. His current interests include the design of USB controllers and imaging periperals. Shi-Yu Huang received his BS, MS degrees in Electrical Engineering from National Taiwan University in 1988, 1992 and Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. From 1997 to 1998 he was a software engineer at National Semiconductor Corp., Santa Clara, investigating the System-On-Chip design methodology. From 1998 to 1999, he was with Worldwide Semiconductor Manufacturing Corp., designing the high-speed Built-In Self-Test circuits for memories. He joined the faculty of National Tsing-Hua University, Taiwan, in 1999, where he is currently an Associate Professor. Dr. Huang’s research interests include CMOS image sensor design, low-power memory design, power estimation, and fault diagnosis methodologies.     

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.     

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.     

Automatic Test Generation for Combinational Threshold Logic Networks

We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling, backed by HSPICE simulations, to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.     

Fault detection in combinational circuits using a compressed fault table

A method is developed for obtaining a highly compressed fault table for two-level combinational circuits. A set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault table. The method is equally suitable for sum of products form or product of sums form realization of logic functions and generates the test set directly from the algebraic expression of the logic function.     

Self-timed is self-checking

Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, andundefined states; the fourth state is used to signal illegal output and is shown to result only from certain circuit faults. The self-timed circuits also employ four-phase signaling according to a well-defined protocol of communications between the circuit and its environment; failures due to certain faults prevent the circuit from communicating properly, thus causing the circuit to halt. We show that any single stuck-at fault falls in either the first or the second category, thus providing complete fault coverage through self checking. No hardware needs to be added to our circuits to achieve the complete self-checking property; further, the circuit is guaranteed to never generate a legal but erroneous output if it contains a fault. Minimal hardware is needed to detect that a circuit has either halted or has generated an illegal output.