组合逻辑多故障诊断

通过对布尔差分法的剖析,得到了组合电路单固定故障测试生成的简化方法。该方法不必进行异或运算,只须求解恒等式就能得到组合逻辑电路的８测试矢量。多故障的测试码产生可以对高阶布差分经过变换,转化为一阶布尔差分来处理,从而极大地减少了多故障测试生成的计算工作量。     

Model for Transient Fault Susceptibility of Combinational Circuits

Transient faults (TFs) are increasingly affecting microelectronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional electrical level simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a new model to estimate accurately the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We will show how the proposed model can be applied in order to estimate the TF susceptibility of a circuit by simply considering the propagation delay of the datapath. Therefore, the proposed model is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to electrical level simulation. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.     

波形模拟器关于组合电路中竞争冒险的应用

为了更好地研究组合逻辑电路的竞争冒险现象,提出了一种关于组合电路竞争冒险的波形模拟方法,利用基于布尔过程的波形模拟器对电路进行模拟.该方法为检测电路中的竞争冒险现象提供了帮助,能有效降低对某些尖峰脉冲敏感的负载电路所产生的影响.实验结果证明了该方法的可行性和有效性.     

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.     

模拟电路故障诊断的新故障字典法

基于节点电压灵敏度,将文献[1]中的线性无容差电路的故障字典法推广到可以诊断容差模拟电路和非线性电路软故障的新故障字典法。讨论了该方法的原理和字典的建立方法,给出了仿真实例。     

Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware

This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the circuit under diagnosis (CUD). This method allows designers to perform dynamic fault location of stuck-at faults in large circuits, and eliminates the need for large storage required by a software-based fault dictionary. In fact, the approach is a pure hardware solution to fault diagnosis. We demonstrate the feasibility of the method in terms of hardware resources and diagnosis time by experimenting with ISCAS85 and ISCAS89 circuits. The emulation-based diagnosis method speeds up the diagnosis process by an order of magnitude compared to the software-based fault diagnosis. This speed-up is important, especially, when the on-line diagnosis of safety–critical systems is of concern.

基于分布估计算法的组合电路测试生成

基于遗传算法生成的测试矢量集的故障覆盖率要低于确定性方法．本文分析指出造成这种现象的一个可能原因在于，组合电路测试生成过程中存在高阶、长距离模式，从而导致遗传算法容易陷人局部极值或早熟收敛．为此，本文首次提出使用分布估计算法生成测试矢量．该方法使用联合概率分布捕捉电路主输人之间的关联性。从而避免了高阶、长距离模式对算法的影响，缓解了算法早熟收敛问题．针对ISCAS-85国际标准组合电路集的实验结果表明，该方法能够获得较高的故障覆盖率．     

模拟数字电路故障诊断新方法

利用小波变换与神经网络相结合的方法,采用能量分布特征提取方法和改进BP算法,给出了一种基于小波变换和BP神经网络相结合的模拟电路故障诊断方法.用正弦信号仿真模拟电路,应用小波变换对模拟电路的采样信号进行多尺度分解,再进行能量分布特征提取,然后利用神经网络对各种状态下的特征向量进行分类识别,实现模拟电路故障诊断.在用神经网络诊断模拟电路的基础上,进行了将神经网络用于数字电路单故障诊断的研究.对两者的实例电路仿真结果表明,神经网络可以有效、方便地实现电路的故障检测和定位,准确率高,为故障诊断的研究提供了一种新思路.     

用可编程逻辑器件进行组合电路设计时的延时分析

随着高校EDA教学的不断深入,学生往往只注重设计工具、编程语言的熟练程度,而忽视了电路设计中的一些基本问题。本文详细分析了组合电路中延时错误产生的原因,并提出了三种解决方法。     

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS’85 and full-scan ISCAS’89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.     

Synthesis and Optimization of Combinational Interface Circuits

We describe an algorithm for interface synthesis and optimization for embedded system components such as microprocessors, memory ASIC, and network subsystems. The algorithm accepts the timing characteristics of two chips as input, and generates a combinational interface circuitry to implement communication between them. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections employing a 0-1 ILP formulation to minimize wiring area and dynamic power consumption in the resulting interface circuit. In the second part, we use a novel encoding method to synthesize connections between chips which require additional gates in the interface circuit. Experiments show that our algorithm is very effective in practice.     

模拟电路故障诊断方法综述

阐述了模拟电路故障诊断的意义,分析了现阶段模拟电路故障诊断的一些常用理论和方法,总结了这些方法的基本原理、特点及发展现状。提出了在模拟电路故障诊断研究中存在的问题,指出了其发展趋势。     

Design Error Diagnosis with Re-Synthesis in Combinational Circuits

A new approach is proposed for removing design errors from digital circuits, which does not use any error model. Based on a diagnostic pre-analysis of the circuit, a subcircuit suspected to be erroneous is extracted. Opposite to other known works, re-synthesis of the subcircuit need not be applied to the whole function of the erroneous internal signal in terms of primary inputs, it may stop at arbitrary nodes inside the circuit. As the subcircuits to be redesigned are kept as small as possible, the speed of the whole procedure of diagnosis and re-synthesis can be significantly increased. A formal algorithm is proposed for the whole procedure. Experimental data show the efficiency of the diagnostic pre-analysis.     

一阶布尔差分在组合逻辑电路测试生成中的应用

文章给出了一阶布尔差分的几种求法,并对这几种方法进行了分析、比较,进而通过具体逻辑电路阐述如何用布尔差分及其性质迅速求出逻辑电路的单故障测试集。     

虚拟项目教学法在组合逻辑电路教学中的应用

本文介绍虚拟项目教学法在组合逻辑电路教学中的应用。综合运用门电路、编码器、加法器、译码器等组合逻辑电路知识完成加法计算器的分析和设计。实践表明,借助Multisim12开展虚拟项目教学能够提高学生的自主学习能力和创新能力。     

组合逻辑电路设计的一种方法

在ASIC设计和PLD设计中组合逻辑电路设计的最简化是很重要的,在设计时常要求用最少的逻辑门或导线实现。在ASIC设计和PLD设计中需要处理大量的约束项,值为1或0的项却是有限的,提出组合逻辑电路设计的一种新方法。该方法不考虑这些约束项,只考虑那些值为1或0的项,因而可以简化设计步骤。该方法特别适合于有大量约束项的组合逻辑电路设计。例举2个组合逻辑电路实例,说明按照这个改进的方法可以大大减少组合逻辑电路设计步骤。     

基于小波神经网络的模拟电路故障诊断方法及LabVIEW实现

采用虚拟仪器开发平台实现了基于小波神经网络的故障诊断系统,以蔡氏电路为例进行故障诊断,通过采用不同的数据处理方法以及不同的神经网络模型,验证了文中所提方法的可行性.人性化的交互界面,可以方便的从虚拟仪器前面板中得到故障的类型和故障的位置.由此可以看出基于虚拟仪器的故障诊断技术具有很强的实用价值.     

组合电路内建自测试技术的研究

随着集成电路技术的发展,可测性设计在电路设计中占有越来越重要的地位,内建自测试作为可测性设计的一种重要方法也越来越受到关注。文中首先介绍了内建自测试的实现原理,在此基础上以八位行波进位加法器为例,详细介绍了组合电路内建自测试的设计过程。采用自顶向下的设计方法对整个内建自测试电路进行模块划分,用VHDL语言对各个模块进行代码编写并在QuartusII软件环境下通过了综合仿真,结果表明此设计合理,对电路的测试快速有效。     

基于SAT的组合电路自动测试向量生成

实现了基于可满足性(SAT)求解的方法,以解决固定型和时延故障的自动测试向量生成问题.详细讨论了如何利用电路的拓扑结构以及从ATPG到合取范式(CNF)的编码方法.CNF被输入到一个高效的SAT求解器zchaff中求解.在ISCAS85测试实例中验证了该算法的有效性.     

基于虚拟可及测试节点的模拟电路故障诊断

针对网络撕裂方法诊断模拟电路故障过程中撕裂节点必须是可及节点的限制,提出了虚拟可及测试节点的方法.利用网络拓扑结构和基尔霍夫电流定律计算一类不可及测试节点故障电压,让其成为虚拟可及测试节点.然后在可及或虚拟可及测试节点对网络进行撕裂,再根据故障电压和故障判据定位故障至更小的区域,从而进一步定位故障元件.这种新方法降低了待诊断电路中对可及节点数目的要求,增加了撕裂的灵活性.通过仿真实例验证了该方法的有效性.