初学者知识园地

它是以金属—氧化物一半导体场效应晶体管为主体构成的集成电路,简称为MOS集成电路。以N型沟道MOS晶体管构成的集成电路,称为N沟MOS集成电路,以P型沟道MOS晶体管构成的集成电路称为P沟MOS集成电路,二者统称单沟MOS电路。 N沟器件的多数载流子是电子,P沟器件的多数载流子是空穴。场效应器件是多数载流子工作的器件,电子比空穴的有效质量小,迁     

Bi-CMOS器件

在相当早以来人们就想把MOS器件和双极型器件制作在同一芯片上组成有效利用其各自的优点补其缺点的电路。其最有代表的产品要算是MOS运算放大器的研制,这种MOS运算     

High-k材料MOS器件的PISCES-II模拟

High-k材料是指介电常数k高于SiO2的材料。使用high-k材料做栅绝缘层,是减小MOS器件栅绝缘层直接隧道击穿(DirectTunneling,DT)电流的有效方法。文章在二维器件模拟软件PISCES-II中添加了模拟以high-k材料为栅绝缘层的MOS器件模型,并对SiO2和high-k材料的MOS晶体管器件特性进行了模拟比较,成功地验证了所加high-k材料MOS器件模型的正确性。改进后的PISCES-II程序,可以方便地对以各种high-k材料为栅绝缘层的器件性能进行模拟。     

用聚焦硼离子束注入到硅中以实现亚微米沟道的MOSFET

用聚焦离子束注入到硅中的一种新型亚微米沟道长度器件—离子束MOSFET(IB—MOS),已显示出聚焦离子束卓有成效的应用。这种器件的有效沟道区域是在源—漏之间As~+注入的N~-栅区用16keV聚焦硼离子束的单线扫描来形成的。(束径:0.2μm、束流密度:50mA/cm~2)。用二维器件的模拟证明了源—漏间距为0.8μm的IB—MOS器件在电流增益、漏极击穿电压和短沟道阈值效应等方面都具有明显的改善。制造出的实     

High-k材料MOS器件的PISCES-Ⅱ模拟

High-k材料是指介电常数k高于SiO2的材料。使用Hihg-k材料做栅绝缘层，是减小MOS器件栅绝缘层直接隧道击穿（Direct Tunneling,DT)电流的有效方法。文章在二维器件模拟软件PISCES－Ⅱ中添加了模拟以high-k材料为栅绝缘层的MOS器件模型，并对SiO2和high-k材料的MOS晶体管器件特性进行了模拟比较，成功地验证了所加high-k材料MOS器件模型的正确性，改进后的PISCES－Ⅱ程序，可以方便地对以各种high-k材料为栅绝缘层的器件性能进行模拟。     

光MOS继电器的交流特性

一、光MOS继电器的特点光MOS继电器的内部结构如图1所示。由图可知光MOS继电器的内部结构与一般的光耦合器件非常相似。其外部开关与封装也与一般的光耦合器件一模一样(照片1)。由发光二极管发射的光经太阳能电池转换成电压,构成MOS场效应管的栅极偏置电压,控制MOS场效应管的通断。输出端用两个MOS场效应管串联连接,可以控制交流信号的通断。与机械触点式继电器相比,光MOS继电器具有     

纳米MOS器件的设计模型

几十年来,MOS器件一直遵循摩尔定律不断发展,对于缩小到纳米尺度的MOS器件,量子效应更加突出。研究纳米尺度MOS器件的物理问题,以及适用于纳米MOS器件的设计已成为当前微电子领域重要研究内容。本文简要介绍和评述了纳米MOS器件的设计模型．并对基于非平衡态格林函数以及薛定谔方程和泊松方程自洽解的器件模型应用进行了举例说明。     

磁敏MOS器件数值模拟及设计优化

本文对磁敏MOS器件进行了计算机模拟,提出用分区域方法进行器件的两维数值分析,有效地降低了计算费用.井利用BFGS方法,对磁敏MOS 器件进行了优化设计,分析结果表明,宽长比W/L为0.82的磁敏器件有最高的灵敏度,实验结果证实了这一理论预测.     

MOS型摄象器件的分析

MOS型固体摄象器件是和CCD并行发展的一种摄象器件,它具有单电源、低功耗、扫描方式灵活等特点,是一种很有实用价值的固体摄象器件.本文主要介绍了MOS型固体摄象器件的工作原理、固定图形噪声及抑制方法、分辨率、读出特性、低速扫描特性及用这种器件组成的摄象系统.     

CCD模拟延迟线在红外系统中的应用

1970年美国贝尔电话实验室的W.S.Bogle和G.E.Smith首先提出了电荷耦合器件(CCD)概念。这是在MOS器件发展的基础上提出的用MOS电容存储的电荷转移来传递信息的概念。根据此概念制成了一种全新的半导体功能器件。由于CCD结构简单,成本低廉,并     

Temperature dependence of Fowler-Nordheim current in 6H- and 4H-SiCMOS capacitors

This work reports on Fowler-Nordheim (F-N) injection studies on n-type 6H-SiC and 4H-SiC MOS systems under positive gate bias from 25 to 325°C. At a given temperature and electric field, the current density in the 4H-SiC MOS system is about five times higher than that in 6H-SiC due to the smaller effective barrier height for the 4H-SiC MOS system as compared to 6H-SiC. The reduction of the effective barrier height with temperature, particularly in 4H-SiC, raises serious concerns about the long-term reliability of gate oxides in SiC. It is concluded that the maximum practical values of electric field in the 4H-SiC MOS system under positive gate bias and high junction temperature should be reduced to below the values used in the Si MOS system     

Effects of wet oxidation/anneal on interface properties ofthermally oxidized SiO2/SiC MOS system and MOSFET's

Effects of wet atmosphere during oxidation and anneal on thermally oxidized p-type and n-type MOS interface properties were systematically investigated for both 4H- and 6H-SiC. Deep interface states and fixed oxide charges were mainly discussed. The wet atmosphere was effective to reduce a negative flatband shift caused by deep donor-type interface states in p-type SiC MOS capacitors. Negative fixed charges, however, appeared near the interface during wet reoxidation anneal. In n-type SIC MOS capacitors, the flatband shift indicated a positive value when using wet atmosphere. The relation between interface properties and characteristics of n-channel planar 6H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) was also investigated. There was little relation between the interface properties of p-type MOS capacitors and the channel mobility of MOSFETs. The threshold voltage of MOSFETs processed by wet reoxidation anneal was higher than that of without reoxidation anneal. A clear relation between the threshold voltage and the channel mobility was observed in MOSFETs fabricated on the same substrate     

Influence of a resistive sublayer at the polysilicon/silicon dioxide interface on MOS properties

We suggest that a thin (≥100 Å) resistive sublayer of polysilicon neat the oxide interface can have a pronounced effect on the MOS capacitances-voltage characteristics. On the depletion side of theC-Vcurve, the lower effective work-function difference leads to a higher threshold for strong inversion. On the accumulation side, the MOS capacitance is lowered due to the added thickness of the depletion sublayer. With the help of the sublayer model, we attempt to explain the anomalous behavior often observed in MOS capacitors with silicide/polysilicon gates. The sublayer depletion activates traps due to the heavy impurities (Cu, Fe, and Ta) at the interface, a considerable amount of which were observed in these samples by Auger spectroscopy.     

Investigation of electron-hole generation in MOS capacitors on 4H SiC

This paper investigates electron-hole generation in n-type MOS capacitors on 4H-SiC with the gate oxide directly grown in either 100% NO or 10% N/sub 2/O. High-temperature capacitance-transient measurements were used to determine and compare the contributions of carrier generation in the bulk and at the SiO/sub 2/-SiC interface. The effective generation rate in the bulk is similar in the MOS capacitors with either type of gate oxide, whereas the effective surface-generation rate is much lower in the case of oxides grown in 100% NO. Moreover, the effective surface-generation rate in these oxides is reduced to the level that is comparable to the effective bulk-generation rate. This result demonstrates the high quality of MOS capacitors with the gate oxide directly grown in 100% NO.     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

MOS器件的质子总剂量效应

介绍了几种加固和非加固 MOS电路的质子辐照总剂量效应实验 ,质子束的能量为 9、 7、 5、 2 Me V.实验结果表明 ,在相同的吸收剂量下 ,MOS器件累积电离辐射损伤与质子能量成正比 .还给出了栅极偏压对器件质子辐射损伤的影响 ,结果认为 ,对于 NMOSFET,不论是加固器件 ,还是非加固器件 ,在 +5 V的栅压偏置下 ,器件的辐射损伤比 0 V栅压下的损伤严重 ,对于加固器件 ,辐射感生界面态的密度也较高 ;而加固型 PMOSFET,在 0 V的栅压下 ,辐射损伤比 - 5 V下严重 ,且界面态的密度高     

利用FN振荡电流测量薄栅MOS结构栅氧化层中隧穿电子的有效质量

给出了一种利用 FN振荡电流的极值 ,测量电子在薄栅 MOS结构的栅氧化层中的平均有效质量方法 .利用波的干涉方法来处理电子隧穿势垒的过程 ,方便地获得了出现极值时外加电压和电子的有效质量之间的分析表达式 .用干涉方法计算所得到的隧穿电子在不同的 MOS结构的二氧化硅介质层中的有效质量表明 :它一般在自由电子质量的 0 .5 2— 0 .84倍的范围 .实验结果表明 :电子有效质量的值不随外加电压的变化而变化 ,并且对于相同的MOS结构 ,电子可能具有相同的有效质量     

The MOS inversion layer as a minority carrier injector

In this paper we report the first experimental demonstration of the concept of MOS inversion layer injection (ILI). The new physical concept is based on the use of a MOS inversion layer as a minority carrier injector as part of a dynamic junction. The carrier injection of such a junction is entirely controlled by the MOS gate. Moreover, when the gate potential is reduced under the MOS threshold voltage, the junction collapses ensuring a very efficient turn-off mechanism. Based on this concept we propose two novel lateral three-terminal structures termed inversion layer diode (ILD) and inversion layer bipolar transistor (ILBT). The concept of inversion layer injection can be applied in power devices where effective MOS gate control of the active junctions is important     

Scaling of MOS technology to submicrometer feature sizes

Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.     

Scaling of MOS technology to submicrometer feature sizes

Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.