深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

亚微米BiCMOS工艺技术

ＢｉＣＭＯＳ是双极的速度和驱动能力与ＣＭＯＳ的高密度和低功耗的结合。考虑到功耗原因，ＢｉＣＭＯＳ器件主要以ＣＭＯＳ为主。因此，双极器件通常并入ＣＭＯＳ核心工艺流程。当器件尺寸减小时，双极和ＣＭＯＳ技术显得愈发相似。本文例举了０．８μｍ和０．５μｍ的技术论点，ＢｉＣＭＯＳ电路与ＣＭＯＳ相比，成本稍有增加，但其性能提高一倍。     

亚微米BiCMOS工艺技术

ＢｉＣＭＯＳ是双极速度和驱动能力与ＣＭＯＳ的高密度和低功耗的结合。考虑到功耗原因，ＢｉＣＭＯＳ器件主要以ＣＭＯＳ为主，因此，双极器件通常并入ＣＭＯＳ核心工艺流程。当器件尺寸减小时，双极和ＣＭＯＳ的技术显得愈发相似。本文列举了０．８μｍ和０．５μｍ的技术论点。ＢｉＣＯＳ电路与ＣＭＯＳ相比，成本稍高但其性能提高一倍。     

一种适合于ASIC应用的新的工艺技术—CMOS逻辑VLSIE^2PROM的单片集成

我们开发了一种新的工艺技术，实现了在ＣＭＯＳ ＶＬＳＩ制造中嵌入Ｅ＾２ＰＲＯＭ的制造技术。在此新工艺中，制造的是单层多晶硅的Ｅ＾２ＰＲＯＭ。与传统的双层多晶硅Ｅ＾２ＰＲＯＭ的工艺相比，减少了２５％的工序。通过采用三种不同厚度的栅氧化层，可以缩小在ＣＭＯＳＶＬＳＩ中嵌入的Ｅ＾２ＰＲＯＭ的器件尺寸。器件工作电压范围宽为１．５－６Ｖ，静态电流低于１００ｎＡ。     

SOIMOS器件的低温特性

本文概述性地探讨了低温ＳＯＩＭＯＳ器件的基本特性，如电流－电压特性、迁移率、阈值电压及亚阈值特性等，并介绍了该器件中所存在的一些效应。     

MOS器件“鸟嘴区”电学特性研究

随着ＭＯＳ器件尺寸的缩小，“鸟嘴区”对窄沟器件的电学特性已产生了明显的影响．本文研究了窄沟器件（Ｗ＝１．２μｍ，２μｍ）中“鸟嘴区”引起的栅电压对有效沟道宽度调制效应以及“鸟嘴”区域内载流子有效迁移率的变化规律，并对窄沟器件模型提出了修正公式．     

深亚微米MOSFET热载流子退化机理及建模的研究进展

本文给出了深亚微米ＭＯＳ器件热载流子效应及可靠性研究与进展,对当前深亚微米ＭＯＳ器件中的主要热载流子现象以及由其引起的器件性能退化的物理机制进行了详细论述。不仅对热电子,同时也对热空穴的影响进行了重点研究,为深亚微米ＣＭＯＳ电路热载流子可靠性研究奠定了基础。本文还讨论了深亚微米器件热载流子可靠性模型,尤其是ＭＯＳ器件的热载流子退化模型。     

短沟道CMOS／SOI器件加固技术研究

通过大量辐照实验分析了采用不同工艺和不同器件结构的薄膜短沟道ＣＭＯＳ／ＳＩＭＯＸ器件的抗辐照特性，重点分析了Ｈ２－Ｏ２合成氧化和低温干氧氧化形成的薄栅氧化层、ＣｏＳｉ２／多晶硅复合栅和多晶硅栅以及环形栅和条形栅对ＣＭＯＳ／ＳＩＭＯＸ器件辐照特性的影响，最后得到了薄膜短沟道ＣＭＯＳ／ＳＩＭＯＸ器件的抗核加固方案．     

高性能BiCMOS制造技术及I/O电路优化

本文报导一套先进的ＢｉＣＭＯＳ集成电路制造技术，建立在ＣＭＯＳ工艺基础上的ＢｉＣＭＯＳ制造工艺，增加了双埋层，２．５微米本征外延层，双阱，基区，多晶硅发射区，深集电区和平坦化双层金属布线等工艺技术。器件性能测试和扫描电镜检查结果表明，双极器件和ＭＯＳ器件性能优良，ＢｉＣＭＯＳ器件的抗锁定性能比ＣＭＯＳ器件提高了一个数量级。     

Very small MOSFET's for low-temperature operation

The improvements in the device characteristics of n-channel MOSFET's that occur at low temperatures are considered in this paper. The device parameters for polysilicon gate FET's with channel lengths of the order of 1 µm have been studied both experimentally and theoretically at temperatures ranging from room temperature down to liquid nitrogen temperature. Excellent agreement was found between the experimental dc device characteristics and those predicted by a two-dimensional current transport model, indicating that device behavior is well understood and predictable over this entire temperature range. A device design is presented for an enhancement mode FET with a channel length of I µm that is suitable for operation at liquid nitrogen temperature.     

Assessment of the Trench IGBT reliability: low temperature experimental characterization

The purpose of this study is an assessment of the Trench IGBT reliability at low temperature under static and dynamic operations by the aim of intensive measurements. The analysis of the Trench IGBT behaviour in these conditions is dedicated to the HEV applications. One question can be raised in case of the use of HEV in countries where during winter the temperature drops down −50 °C or less: are Trench IGBT strongly affected by the low temperature environment? In this paper, we present experimental results under various test conditions (temperature, gate resistance, voltage and current) to give an understanding of the device behaviour by focusing on the device current and voltage waveforms and the power losses.     

正交块循环矩阵在多路寻址液晶驱动中的应用

传统的多路寻址液晶驱动矩阵电路设计规模与矩阵阶数平方成正比。研究表明:由正交块循环矩阵构造出的多路寻址驱动矩阵的实现复杂度由原来的与矩阵的阶数平方成正比下降为与矩阵的阶数成正比。分析正交块循环矩阵特性后,介绍了基于类单位矩阵的系统化构造正交块循环矩阵的方法。在多行(COMMON)快速帧频响应的多路寻址液晶驱动设计中采用正交块循环矩阵可大大降低实现成本。     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

Super thin-film transistor with SOI CMOS performance formed by anovel grain enhancement method

High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity     

Electrically driven uniaxial stress device for tuning in situ semiconductor quantum dot symmetry and exciton emission in cryostat

Uniaxial stress is a powerful tool for tuning exciton emitting wavelength, polarization, fine-structure splitting (FSS), and the symmetry of quantum dots (QDs). Here, we present a technique for applying uniaxial stress, which enables us in situ to tune exciton optical properties at low temperature down to 15 K with high tuning precision. The design and operation of the device are described in detail. This technique provides a simple and convenient approach to tune QD structural symmetry, exciton energy and biexciton binding energy. It can be utilized for generating entangled and indistinguishable photons. Moreover, this device can be employed for tuning optical properties of thin film materials at low temperature.     

可制造性设计在纳米SOC中的应用和发展

随着图形特征尺寸的不断缩小、集成度的不断提高,集成电路已进入纳米系统芯片(SOC)阶段,摩尔定律依靠器件尺寸缩小得以延续的方式正面临着众多挑战。分析了纳米SOC中影响性能和良品率的关键效应及相应的措施。从半导体产业链的发展演变指出了可制造性设计(DFM)是纳米SOC阶段提高可制造性与良品率的解决方案。与光刻性能相关的分辨率增强技术(RET)是推动DFM发展的第一波浪潮,下一代的DFM将更注重良品率的受限分析及设计规则的综合优化。综述了DFM产生的历史及发展的现状,并对其前景进行了展望。     

Investigation of thermal effects in quantum-cascade lasers

The development of a thermal model for quantum cascade lasers (QCLs) is presented. The model is used in conjunction with a self-consistent scattering rate calculation of the electron dynamics of an InGaAs-AlAsSb QCL to calculate the temperature distribution throughout the device which can be a limiting factor for high temperature operation. The model is used to investigate the effects of various driving conditions and device geometries, such as epilayer down bonding and buried heterostructures, on the active region temperature. It is found that buried heterostructures have a factor of eight decrease in thermal time constants compared to standard ridge waveguide structures in pulsed mode and allow a /spl sim/78% increase in heat sink temperature compared to epilayer down mounted devices in continuous-wave mode. The model presented provides a valuable tool for understanding the thermal dynamics inside a quantum cascade laser and will help to improve their operating temperatures.     

Statistical Design of Low Power Square-Law CMOS Cells for High Yield

A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.