Mechanism analysis of gate-induced drain leakage in off-state n-MOSFET

An analytical expression for both band-to-band and band-trap-band indirect tunnelings is used to study the gate-induced drain leakage (GIDL) current of MOSFETs measured before and after hot-carrier stress. The voltage and temperature dependence of GIDL are characterized. Both results show that interface traps situated near the midgap participate in the conduction of GIDL, and band-trap-band indirect tunneling could be the major mechanism. This is further supported by the fact that the percentage increase in GIDL induced by hot-carrier stress is about the same as the corresponding increase in interface-trap density. On the other hand, under low-field conditions, trap-assisted Poole–Frenkle emission dominates over tunneling for temperatures even well below room temperature.     

Gate current in self-aligned n-channel and p-channel pseudomorphicheterostructure field-effect transistors

A report is presented on the results of the study of the gate leakage current in n-channel and p-channel self-aligned pseudomorphic HIGFETs. The authors demonstrate that in these devices the gate leakage current is practically independent of the gate length. This means that the gate current primarily flows into the source and drain contacts through small sections of the channel near the contacts. At large gate voltages, the gate current is limited by the band discontinuities at the heterointerface, similar to the gate current in non-self-aligned heterostructure field-effect transistors     

Subthreshold drain leakage currents in MOS field-effect transistors

There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (Vtx) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage Vi, the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between Viand Vtxthe surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below Vtx. The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.     

High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.     

Enhanced off-state leakage currents in n-channel MOSFETs withN2O-grown gate dielectric

This paper reports on the off-state drain (GIDL) and gate current (Ig) characteristics of n-channel MOSFETs using thin thermal oxide (OX), N₂O-nitrided oxide (N2ON), and N₂O-grown oxide (N20G) as gate dielectrics. Important phenomena observed in N20G devices are enhanced GIDL and Ig in the low-field region as compared to the OX and N20N devices. They are attributed to heavy-nitridation-induced junction leakage and shallow-electron-trap-assisted tunneling mechanisms, respectively. Therefore, N2ON oxide is superior to N20G oxide in leakage-sensitive applications     

High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions

A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.     

Analysis of leakage currents and impact on off-state powerconsumption for CMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications     

Analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs for circuit simulation

An analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs is presented. A simple polynomial approximation is used to model the sheet carrier concentration (p/sub s//sup H/) in the two-dimensional hole gas at the Si/SiGe interface. The interdependence of p/sub s//sup H/ and the hole concentration at the Si/SiO/sub 2/ interface (p/sub s//sup S/) is taken into account in the model, which considers current flow at both the Si/SiGe and the Si/SiO/sub 2/ interfaces. This model is applicable to compressively strained SiGe buried-channel heterostructure PMOSFETs as well as tensile-strained surface-channel PMOSFETs. The model has been implemented in SABER, a circuit simulator. The results from the model show an excellent agreement with the experimental data.     

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress

In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress.     

New observation and the modeling of gate and drain currents inoff-state P-MOSFET's

The work reports new observations concerning the gate and drain currents measured at off-state conditions in buried-type p-channel LDD MOSFET devices. Detailed investigation of the observed phenomena reveals that 1) the drain current can be separated into two distinct components: band-to-band tunneling in the gate-to-drain overlap region and collection of holes generated via impact ionization by electrons inside the oxide; and 2) the gate current can be separated into two distinct components: the hot electron injection into the oxide and the Fowler-Nordheim electron tunneling through the oxide, At low negative drain voltage, the dominant component of the drain current is the hole generation inside the oxide. At high negative drain voltage, the drain current is essentially due to band-to-band tunneling, and it is correlated with the hot-electron injection-induced gate current     

Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors

The merging of halo implants from the drain side and the source side creates a maximum in the magnitude of the threshold voltage and thus a minimum in the off-current in the metal-oxide-semiconductor transistors. This paper demonstrates that the halo implant from the drain side can cross-over to the source side and vice versa for the look-ahead transistor test structures (transistor test structures with gate length smaller than that of the target transistor). The phenomenon of the cross-over of halo implant is more readily observed in PMOS transistors compared to NMOS transistors because for the same mask gate length, the effective channel length of PMOS transistor tends to be smaller than that of NMOS transistor. The advantage of the cross-over of halo implants can be understood as follows. Since the hole mobility is smaller than the electron mobility in silicon, PMOS transistor tends to have smaller on-current (I_on) than NMOS transistor. The on-current can be increased by using PMOS transistor with smaller mask gate length compared to the NMOS transistor. However, this approach will make the PMOS transistor very sensitive to the statistical variation in the gate electrode length during manufacturing. By making use of the above reported phenomenon, PMOS transistor can be made shorter without running into manufacturing control problem, resulting in bigger I_on but the penalty is that the I_off will become significantly higher.     

Low-frequency noise in p-channel heterostructure insulated-gatefield-effect transistors (HIGFETs) at 77 K and drain current 1μA

Measurements of the low-frequency spectral intensity of the current fluctuations in p-channel GaAs/AlGaAs heterostructure insulated-gate field-effect transistors are discussed. The measurements were performed at 77 K and a drain current of 1 μA. The spectra of two types of devices are compared, one grown directly on the substrate and the other embedded in an n-well. The latter type produced markedly less noise, its spectrum being almost perfect 1/f noise. The former type exhibited, in addition to the 1/f noise, a significant generation-recombination noise component in the spectrum     

An analytic saturation model for drain and substrate currents ofconventional and LDD MOSFETs

An analytic saturation model for conventional and lightly doped drain (LDD) MOSFETs is developed by using the pseudo-two-dimensional approximation in the channel and drain regions to obtain both the channel length modulation factor and the maximum electric field. Using the established I-V model in the linear region, the drain currents of conventional and LDD MOSFETs can be explicitly calculated. The substrate currents of conventional/LDD MOSFETs are calculated by using an existing simplified substrate current formula and the maximum electric field model. It is shown that the accuracy of the maximum electric field is acceptable for calculating the substrate currents of conventional/LDD MOSFETs. The parameters used in the model can be determined by the existing extraction methods and the optimization technique. The saturation model is shown to be valid for a wide range of channel lengths and bias conditions     

Distortion in off-state arsenide MESFET switches

This paper presents the results of an investigation into the origin and level of distortion generated by the off-state gallium arsenide MESFET when used as a microwave semiconductor control element. The results show that the drain-gate and gate-source capacitance nonlinearities generate distortion in the device in its off-state. These nonlinearities, which reflect the capacitance-voltage characteristic of the capacitances, can be reduced in as-fabricated devices by increasing the gate reverse bias voltage. The level of distortion monotonically increases with frequency throughout the usable range of the MESFET when used in a series reflective switch. In an SPDT switch application, where both on and off-state devices are used, the distortion level is relatively constant at frequencies in the vicinity of the gate bias cut-off frequency. The nonlinear off-state model is compared with both a SPICE-based analysis, and with experimental data on a GaAs MESFET SPDT switch. The main conclusions to be drawn from the study are that the dominate distortion generated by a GaAs MESFET used in a switch application occurs in the on-state, and that off-state distortion can be only slightly improved in as-fabricated devices     

Hot-carrier-induced off-state current leakage in submicrometerPMOSFET devices

Hot-carrier-induced off-state leakage (HCIOL) currents were successfully used as a new monitor in characterizing device reliability. HCIOL current increases drastically with reducing channel length, but the stress bias only affects the onset time of HCIOL current. For buried-channel PMOSFET's, only the HCIOL currents at the reverse measurement configuration were dominant. However, in surface-channel devices, HCIOL currents at both forward and reverse configurations became important. An empirical HCIOL current model was developed to quantify device lifetime as a function of channel length and stress voltage. Estimated lifetime results indicated that HCIOL current will impose a major limit on device reliability especially for deep-submicrometer technology and low power applications     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

SiGe source/drain structure for the suppression of theshort-channel effect of sub-0.1-μm p-channel MOSFETs

A bandgap engineering technique is proposed for the suppression of the short-channel effect (SCE) and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation. The drain-induced barrier lowering (DIBL) and the charge sharing are suppressed by the presence of the valence band discontinuity between the SiGe source/drain and Si channel. In order to obtain the full advantage of this structure, it is necessary to locate the SiGe layers both at the source/drain regions and the SiSe/Si interface at the pn junction or inside the channel region. The effectiveness increases with the increase of the valence band discontinuity (Ge concentration). As a result of the suppression of the SCE and the reduction of the minimum gate length, the drain current increases, and thus high-speed operation can be realized with this technique     

New observation of gate current in off-state MOSFET

For a gate-controlled p⁺-n diode having gate-p⁺ overlap area of 3.7×10^-4 cm², the author reports a new observation of the leakage currents through a 235-Å gate oxide. The gate current components both due to Fowler-Nordheim electron funneling through the gate-p⁺ overlap oxide and due to hot-electron injections were separately detected. The corresponding gate current was found to be dominated by Fowler-Nordheim electron funneling prior to significant surface avalanche impact ionization     

Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

MOCVD-grown AlInAs/GaInAs MODFET with drain currents higher than 1.3 mA/mm

Very high-density and high-mobility AlInAs/GaInAs modulation-doped heterostructures have been successfully grown by low-pressure MOCVD. FETs, having gate-lengths of 0.25 mu m, fabricated from these heterostructures show transconductances as high as 700 mS/mm, and drain saturation currents in excess of 1.3 mA/mm at V/sub gs/=0 V. This current density is among the highest yet reported for FETs grown by any technique. The extracted current-gain cutoff frequency is 78 GHz.<>