量子全加器设计

量子全加器是量子计算机的基本单元,为了减少能耗,降低构造成本及物理实现难度,本文提出一种新型n位量子全加器,使用3n个CNOT（Controlled NOT）门和2n-1个Toffoli门实现n位量子加减法,采用超前进位方式,不含进位输入,通过最高溢出标志位判断加法的进位和减法的正负号,标志位不参与高低位计算,不增加电路延时,适合n位量子并行计算.随机生成4、8、16和32位数分别进行加减仿真操作,验证了全加器的正确性.该全加器量子代价较低,结构简单,有利于提高集成电路规模和集成度.     

量子全加器构造的探讨

本文探讨了由Toffoli门和受控非门等量子逻辑门构成低位输入、低位输出的量子全加器的电路，并分析了该种量子全加器的变换操作。通过比较推导出有多位输入、多位输出量子全加器的电路组合规律．     

基于T门的2-5混值/十值加、减运算电路设计

本文通过对编码技术的研究,提出采用2-5混值编码方案研究十值运算电路;在电路具体实现过程中,借用T运算,设计2-5混值/十值T门;然后,在此基础上,按真值表直接设计2-5混值/十值全加器和全减器的运算电路.最后用PSPICE模拟验证所设计的电路具有正确的逻辑功能.     

全加器功能及应用的仿真设计分析

加法运算是数字系统中最基本的算术运算.为了能更好地利用加法器实现减法、乘法、除法、码制转换等运算,提出用Multisim虚拟仿真软件中的逻辑转换仪、字信号发生器、逻辑分析仪,时全加器进行功能仿真设计、转换、测试、分析,强化Multisim的使用,并通过用集成全加器74LS283实现两个一位8421码十进制数的减法运算,...     

基于选择进位32位加法器的硬件电路实现

为了缩短加法电路运行时间,提高FPGA运行效率,利用选择进位算法和差额分组算法用硬件电路实现32位加法器,差额分组中的加法单元是利用一种改进的超前进位算法实现,选择进位算法可使不同的分组单元并行运算,利用低位的运算结果选择高位的进位为1或者进位为零的运算结果,节省了进位选择等待的时间,最后利用XILINX进行时序仿真,在FPGA上进行验证,可稳定运行在高达50兆的频率,理论分析与计算机仿真表明该算法切实可行、有效并且易于实现。     

基于改进五输入择多门的QCA全加器设计及应用

量子元胞自动机(Quantum-dot cellular automata,QCA)是一种新兴的纳米技术.本文基于改进的五输入择多门,设计出一个全加器,在保持正确逻辑功能的基础上较以往的全加器有一定优势.应用该全加器设计加法器和乘法器,结果表明在某些性能上有显著提高.     

基于InP DHBT工艺的32.2GHz超高速全加器

介绍了一种基于0.7μm磷化铟(InP)双异质结双极型晶体管(DHBT)工艺的超高速全加器,将加法运算与数据同步锁存融合设计来提高计算速度,采用多数决定运算法则设计单层晶体管并联型进位电路来降低功耗。测试结果表明,全加器的最高时钟频率达32.2 GHz,包含锁存器的全加器整体电路功耗为350 mW。     

CMOS集成电路应用讲座——第六讲 CMOS运算电路

CMOS运算电路可以分逻辑运算电路和算术运算电路两类,C660四异或门和C663四位数字量值比较器是逻辑运算电路中两个典型的电路.算术运算电路包括C661双全加器、C662四位超前进位全加器、CH14560 NBCD全加器及CH14561"9"补码电路和J690 BCD比例乘法器等.     

先行进位光学并行多位全加器的研究

将二进制数的先行进位全加器的逻辑操作引入到光计算中,提出了用光学并行处理方法实现先行进位全加器逻辑操作的建议。信号以空间阵列方式编码,利用空间逻辑阵列,实现并行逻辑操作。研究了PD-LED的光电混合逻辑操作,利用PD—LED逻辑器件,从实验上验证了先行进位光学并行多位全加器,获得了满意的结果。     

64位超前进位对数加法器的设计与优化

设计一个应用于高性能微处理器的快速64位超前进位对数加法器.通过分析超前进位对数加法器原理,提出了改进四进制Kogge-Stone树算法的64位超前进位对数加法器结构,并结合使用多米诺动态逻辑、时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路.该加法器采用SMIC 0.18 μm CMOS工艺实现,在最坏情况下完成一次加法运算时间为486.1 ps,与相同工艺和相同电路结构采用静态CMOS实现相比,大大减少了加法器各级门的延迟时间,取得良好的电路性能.     

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.     

Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays than the existing designs.     

Novel designs for fault tolerant reversible binary coded decimal adders

Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.     

基于多数决定逻辑非门的低功耗全加器设计

全加器是算术运算的基本单元,提高一位全加器的性能是提高运算器性能的重要途径之一。首先提出多数决定逻辑非门的概念和电路设计,然后提出一种基于多数决定逻辑非门的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,较少的管子、工作于极低电源电压、短路电流的消除是该全加器的三个主要特征。对这种新的全加器,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。     

RTD多值逻辑(MVL)电路

RTD具有双稳和自锁特性,用RTD构成电路可节省大量器件,这一优点在构建多值逻辑电路(MVL RTD)时显得尤为突出。在引用"遏止"概念的基础上介绍了几种典型的MVL RTD电路,包括多幅输入脉冲信号具有选幅功能的文字逻辑门、能提供三个不同电平输出的三态反相器、将一输入斜坡电压信号变成脉冲输出信号的折线量化器等电路;用"遏止"概念分析了异或门电路的工作原理。     

基于RRAM双交叉阵列结构的三值存内逻辑电路设计

在RRAM交叉阵列结构中实现逻辑运算可以较好地解决传统冯诺依曼架构中的存储墙问题.三值逻辑相比于传统的二值逻辑,具有更少的逻辑操作数目和更快的运算速度.文中提出了一种基于RRAM双交叉阵列结构的三值存内逻辑电路设计,其中三值逻辑电路的输入与输出均通过多值RRAM的阻值表示.该结构支持两种三值逻辑门和一种二值逻辑门以提升...     

对称三进制光学加法器的进位直达通道设计

以对称三进制光学半加器为基础,提出了一个对称三进制光学全加器方案。主要介绍了进位直达并行通道在对称三进制光学全加器中的实现方案和工作原理,从而论证了实现对称三进制光学全加器的可行性。     

Threshold logic circuit design of parallel adders using resonanttunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed     

基于最小混乱度的三值可逆逻辑综合算法

 三值可逆逻辑综合是可逆逻辑综合的延伸和扩展.为了简化可逆网络,提高三值可逆逻辑门的通用性,对现有三值可逆控制门控制位的生效值扩展为0、1和2.在此基础上提出了基于最小混乱度原则的三值可逆逻辑综合算法.该算法根据三值可逆函数计算其对应真值表中每个变量的相对混乱度和绝对混乱度,以最小混乱度原则选取三值可逆逻辑门,直至真值表中的每个变量的混乱度为零,得到三值可逆网络.该算法的时间复杂度为O(n²×3ⁿ),空间复杂度为O(n×3ⁿ).实验结果表明,与现有已知算法对比,平均门数更少.