Low-power MIMO signal processing

In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.     

基于HP VEE的MDTF数字调谐式射频跳频滤波器自动调试系统设计

在介绍数字调谐式射频跳频滤波器电路结构设计原理的基础上,描述了以HP VEE软件平台和GPIB接口技术构建的MDTF数字调谐式射频跳频滤波器的自动调试系统的设计原理,该系统在研制MDTF数字调谐式射频跳频滤波器的过程中,完成了矫正、候选生成、测试、筛选、在线测试、离线测试等6大部分的调试功能。     

Diagnosis and correction of multiple logic design errors in digitalcircuits

This paper presents a technique to correct multiple logic design errors in a gate-level netlist. A number of methods have been proposed for correcting single logic design errors. However, the extension of these methods to more than one error is still very limited. We direct our attention to circuits with a low multiplicity of errors. By assuming different error dependency scenarios, multiple errors are corrected by repeatedly applying a single error search and correction algorithm. Experimental results on correcting double-design errors and triple-design errors on ISCAS and MCNC benchmark circuits are included     

以实物型电子作品为导向的高职应用电子技术专业毕业设计的实践探索

基于高职应用电子技术专业毕业设计的必要性,简单介绍了毕业设计的形式与内容,总结提出了以实物型电子作品为代表的毕业设计新探索,针对其开展与保障、特点与创新进行了论述与说明,最后指出了现存问题与整改措施。实践表明,开展好实物型电子作品的毕业设计可以提升专业综合实力与技能水平,有利于毕业生就业或创业。     

Asynchronous near-far resistant DS-CDMA receivers without a priorisynchronization

Several receivers for data demodulation in an asynchronous direct-sequence code-division multiple access (DS-CDMA) system operating without prior knowledge of the propagation delays are proposed and compared. Special attention is paid to the near-far problem, and the proposed schemes are numerically shown to be near-far resistant. The near-far resistance is obtained by estimating the a priori unknown propagation delay using a subspace-based technique. Quantities obtained in the estimation procedure are used to design a filter used for suppression of interference, according to the minimum mean square error criterion. Either a decision feedback technique or a simple two-state Viterbi algorithm is subsequently used for the data demodulation in the uncoded case. By extending the trellis used in the Viterbi algorithm, error correcting coding is easily implemented     

一种基于GPS的校时系统

为了实现车站到发通告系统中主站时间的高精度校正,介绍了一种基于GPS的时间校正系统。在分析了GPS系统的特点及其时间同步原理的基础上,采用GPS接收模块GSU-36AF设计了硬件电路,并给出了软件实现及其工作过程。实验结果表明,GPS校时系统工作正常、性能稳定,能够提供精确的时间,具有良好的应用前景。     

飞机着陆道面段运动参数图像测量技术

介绍了利用数字高速摄影机组网测量飞机着陆道面段运动参数的方法.采用凝视测量方法,通过对飞机着陆点位置的统计,正确选取测量区域,合理布设测量站点;并利用多台摄影机联合组网等措施扩展测量范围,解决了由于飞行员难以把握着陆点位置而失去对关键点的测量问题.同时,应用摄影测量原理,通过对摄影机的标校,获得了摄影机的参数;利用图像的数字微分纠正原理,对所摄图像进行修正和重建,得到摄影机的正摄影像,进而利用图像处理方法对起落架机轮及机身测量标志进行基于亚像素的跟踪判读;对判读数据进行处理,得到了飞机着陆道面段的运动轨迹、速度等数据.结合真实飞行试验对测量结果进行了分析,数据结论准确.     

"电子产品设计"课程教学的重要内容

从工程设计实际出发,指出了现行"电子产品设计"课程教学中容易被忽视的重要内容——工程设计控制程序,结合标准分析了设计控制程序的各项内容,包括工作程序、设计输入控制、设计过程控制、设计输出控制、设计更改控制、技术服务和记录,并明确了具体的内在要求,对设计课程的适用性和实用性,以及提高学生电子产品设计能力具有较重要作用和意义。     

点状屏彩色显示管校正透镜优化设计

本文在条状屏彩色显象管校正透镜设计的基础上，提出了蹼状屏彩色显示管校正透镜的优化设计方法并给出了设计实例，通过计算机模拟电子束轨迹和光线追迹，分析了校正透镜面型修正程序的精度。     

Multiple error detection and correction based on redundant residue number systems

This paper presents some results on multiple error detection and correction based on the Redundant Residue Number System (RRNS). RRNS is often used in parallel processing environments because of its ability to increase the robustness of information passing between the processors. The proposed multiple error correction scheme utilizes the Chinese Remainder Theorem(CRT) together with a novel algorithm that significantly simplifies the error correcting process for integers. An extension of the scheme further reduces the computational complexity without compromising its error correcting capability. Proofs and examples are provided for the coding technique.     

飞控计算机的抗干扰性设计

分析了基于DSP技术开发设计的无人机飞控计算机系统可能存在的电磁干扰问题,探讨了在硬件和软件2个方面进行抗干扰性设计的常用措施,采用的硬件抗干扰技术包括:滤波技术、屏蔽技术、隔离技术和良好的接地技术及PCB设计时的必要措施;采用的软件抗干扰技术有:数字滤波、重复检测与输出、软件陷阱、指令冗余及软硬件结合的“看门狗”技术。最后结合系统现场调试过程中遇到的干扰现象,给出了一种快速分析排查由干扰引起的故障的方法,使系统各项设计更加合理,更易于工程实现。     

Phase error correcting vector modulator for personal communications network (PCN) transceivers

A technique is reported for correcting phase errors in vector modulators for application in PCN (personal communication network) transceivers. The technique uses an AM demodulation process to extract the phase error from the output signal, and uses the capability of direct digital frequency synthesisers to predistort the phase of the inphase and quadrature components separately. The phase predistortion method can achieve accuracies of less than 0.05 degrees phase error, which can be further improved by increasing the number of bits in the synthesis.<>     

Analysis of the control vector structure in analog networks design

The methodology of analog networks design developed on the basis of the optimum control theory is used for determining the vector structure controlling the optimization process. The analysis of control vector structure is performed by using the Lyapunov function concept of design process. The investigation of behavior of this function and its time derivative makes it possible to determine optimal switching points of the control vector. Such an approach allows us to minimize the total processor time of network design by correcting the control vector structure in terms of the characteristics of the initial period of design. Numerical results of the optimization process of networks with arbitrary number of transistors indicate the possibility of design process control for minimization of the total processor time.     

瞬时频率指示器的频率校正

分析瞬时频率指示器的频率校正技术,着重介绍了相位的温度漂移的校正,借鉴传统的温度校码方法,提出一种以常温编码为基础,以编码移动和扩展为手段的低位扩展校正技术,彻底解决了相位的温度漂移造成的测频错误,同时大大地减少了调试的工作量。     

Doppler-corrected differential detection of MPSK

An open-loop technique is presented for estimating and correcting Doppler frequency shift in an M-ary differential phase-shift-keyed (MDPSK) receiver. The novelty of the scheme is based on the observation that whereas the change in phase of the received signal over a full symbol contains the sum of the data (phase) and the Doppler-induced phase shift, the same change in phase over half a symbol (within a given symbol interval) contains only the Doppler-induced phase shift. Thus, by proper processing, the latter can be estimated and removed from the former. Analytical and simulation results are given for the variance of the above estimator, and the error probability performance of the MDPSK receiver is evaluated in the presence of the Doppler correction. Next, the practical considerations associated with the application of this technique on bandlimited Nyquist channels are discussed and incorporated into the final design. It is shown that the receiver can, in the absence of timing jitter, be designed to allow combined Doppler correction and data detection with no penalty due to intersymbol interference (ISI). The effects of ISI due to timing jitter are assessed by computer simulation     

空间外差光谱仪干涉图修正研究

空间外差光谱技术（Spatial heterodyne spectroscopy, SHS）是一种新型的光谱分析技术,本文基于空间外差光谱仪的基本原理和特点,研究了实际测量中干涉仪两光臂不平衡造成的畸变干涉图的修正方法,模拟计算了干涉仪两光臂不平衡时干涉图的强度变化,并对其进行了模拟修正,修正后的干涉图与理想的SHS干涉图一致性较好。修正方法主要是测量干涉图的非调制项（即未发生干涉时单个光臂的光强）,以及在干涉图数据处理中引入了一个修正因子。通过对干涉仪两臂不平衡的修正,可以有效地提高干涉图反演光谱的精度。     

AIRMAIL: A link-layer protocol for wireless networks

This paper describes the design and performance of a link-layer protocol for indoor and outdoor wireless networks. The protocol is asymmetric to reduce the processing load at the mobile, reliability is established by a combination of automatic repeat request and forward error correction, and link-layer packets are transferred appropriately during handoffs. The protocol is namedAIRMAIL (AsymmetrIc Reliable Mobile Access In Link-layer). The asymmetry is needed in the design because the mobile terminals have limited power and smaller processing capability than the base stations. The key ideas in the asymmetric protocol design consist of placing bulk of the intelligence in the base station as opposed to placing it symmetrically, in requiring the mobile terminal to combine several acknowledgments into a single acknowledgment to conserve power, and in designing the base stations to send periodic status messages, while making the acknowledgment from the mobile terminal eventdriven. The asymmetry in the protocol design results in a one-third reduction of compiled code. The forward error correction technique incorporates three levels of channel coding which interact adaptively. The motivation for using a combination of forward error correction and link-layer retransmissions is to obtain better performance in terms of end-to-end throughput and latency by correcting errors in an unreliable wireless channel in addition to end-to-end correction rather than by correcting errors only by end-to-end retransmissions. The coding overhead is changed adaptively so that bandwidth expansion due to forward error correction is minimized. Integrity of the link during handoffs (in the face of mobility) is handled by window management and state transfer. The protocol has been implemented. Experimental performance results based on the implementation are presented.     

基于NIOS II的高速实时非均匀性校正

摘要：实时非均匀性校正是红外应用领域的关键技术之一。针对目前公开发表的论文中，非均匀性校正模块化设计程度不高和利用现场可编程门阵列(FPGA)进行校正，速度设计探讨不够深入等问题，展开了深入的研究，最后巧妙地引入NIOS II软核微处理器解决了模块化设计问题，并对速度设计进行了深入的探讨。经过优化设计，校正模块能以111．51MHz的高速实时地进行校正，具有很大的工程应用价值。     

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.     

Burst Erasure Correcting LDPC Codes

In this paper low-density parity-check (LDPC) codes are designed for burst erasure channels. Firstly, lower bounds for the maximum length erasure burst that can always be corrected with message-passing decoding are derived as a function of the parity-check matrix properties. We then show how paritycheck matrices for burst erasure correcting LDPC codes can be constructed using superposition, where the burst erasure correcting performance of the resulting codes is derived as a property of the stopping set size of the base matrices and the choice of permutation matrices for the superposition. This result is then used to design both single burst erasure correcting LDPC codes which are also resilient to the presence of random erasures in the received bits and LDPC codes which can correct multiple erasure bursts in the same codeword.