Flip-chip packaging solution for CMOS image sensor device

Chip scaled opto-electronic packaging is introduced as a cost and size effective packaging solution for mobile phone with built in camera. The chip scaled assembly includes gold bumped CMOS image sensor device and its flip-chip bonding on substrate using the anisotropic conductive material. Two types of flip-chip module were designed to have flip-chip on flex and flip-chip on glass. It is shown that well controlled bumping process of thin film deposition and wet etching gives no damage to image sensing surface during the deposition and stripping of metal film. As results, smart and high degree miniaturized image sensor module is actualized for mobile phone and the reliability test results proved the robustness of module structure having flip-chip. Solder bumping was also reviewed and successfully introduced to verify the alternative of image sensor bumping.     

Design of a novel chip on glass package solution for CMOS image sensor device

This paper presents a chip-on-glass (COG) package solution for CMOS image sensors based on highly precise and reliable bumping and flip-chip bonding techniques. The package is fabricated using three core techniques, namely the damage-free image sensor bumping technique, the wafer form glass substrate patterned technique, and the damage-free flip-chip bonding technique. Since the proposed package concept is new, the effects of the package geometry and material properties on the package reliability are uncertain in the initial design stage. A three-dimensional nonlinear finite element model of the proposed CMOS image sensor package is created. In the simulations, the applied thermal load is cooled from 200 °C to ambient temperature (25 °C) to model the thermal deformation and warpage of the package during the practical ACF assembly cooling process. The design parameters influencing the reliability of the package, i.e. the material properties of the ACF, the thickness of the image chip and the thickness of the optical glass are investigated. Two control levels are specified for the chip, glass, and ACF factors and a 2³ factorial design is created to determine the appropriate combination of material properties and geometric size. It is found that the glass thickness and the ACF properties significantly affect the thermal deformation of the package, while the chip and glass factors, and the interaction between them, significantly affect the warpage. Regression models are developed to perform a series of surface response simulations. Using the developed statistical tests and regression models, suitable material selection criteria and geometric sizes can be specified to satisfy various reliability considerations in the initial design stage.     

A pixel size shrinkage of amplified MOS imager with two-line mixing

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm². Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively     

Highly reliable flip-chip-on-flex package using multilayered anisotropic conductive film

Anisotropic conductive film (ACF) has been used as interconnect material for flat-panel display module packages, such as liquid crystal displays (LCDs) in the technologies of tape automated bonding (TAB), chip-on-glass (COG), chip-on-film (COF), and chip-on-board (COB). Among them, COF is a relatively new technology after TAB and COG bonding, and its requirement for ACF becomes more stringent because of the need of high adhesion and fine-pitch interconnection. To meet these demands, strong interfacial adhesion between the ACF, substrate, and chip is a major issue. We have developed a multilayered ACF that has functional layers on both sides of a conventional ACF layer to improve the wetting properties of the resin on two-layer flex for better interface adhesion and to control the flow of conductive particles during thermocompression bonding and the resulting reliability of the interconnection using ACF. To investigate the enhancement of electrical properties and reliability of multilayered ACF in COF assemblies, we evaluated the performance in contact resistance and adhesion strength of a multilayered ACF and single-layered ACF under various environmental tests, such as a thermal cycling test (−55°C/+160°C, 1,000 cycles), a high-temperature humidity test (85°C/85% RH, 1,000 h), and a high-temperature storage test (150°C, 1,000 h). The contact resistance of the multilayered ACF joint was in an acceptable range of around a 10% increase of the initial value during the 85°C/85% RH test compared with the single-layered ACF because of the stronger moisture resistance of the multilayered ACF and flex substrate. The multilayered ACF has better adhesion properties compared with the conventional single-layered ACF during the 85°C/85% RH test because of the enhancement of the wetting to the surface of the polymide (PI) flex substrate with an adhesion-promoting nonconductive film (NCF) layer of multilayered ACF. The new ACF of the multilayered structure was successfully demonstrated in a fine-pitch COF module with a two-layer flex substrate.     

A 2/3-in 400k-pixel sticking-free stack-CCD image sensor

A 2/3-in 400k-pixel stack-CCD image sensor overlaid with an amorphous silicon photoconversion layer has been developed with FIT architecture. The image sticking, which occurred under 10000× standard-incident light conditions, is completely suppressed to the invisible level with bias charge injection operation into the a-Si photoconversion layer. Furthermore, the fixed pattern noise (FPN) of 30 electrons_p-p at 60°C has been achieved by 0.6-V biased storage diodes     

A 1 K×1 K high dynamic range CMOS image sensor with on-chipprogrammable region-of-interest readout

An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm² and the total chip area is 164 mm ²     

TAB器件的电特性分析

本文介绍了自动带焊（ＴＡＢ）器件的载带结构及其电参数，构造了集中参数的等效电路．用ＰＳＰＩＣＥ程序对ＴＡＢ器件和引线键合器件的高频特性进行分析和对比后，阐明了ＴＡＢ器件在高频特性方面优于传统封装形式的器件。通过长线模型，模拟了ＴＡＢ器件的延时特性；并分析了ＴＡＢ器件的热特性。     

Design and testing of a kinematic package supporting a 32×32array of GaAs MQW modulators flip-chip bonded to a CMOS chip

Innovative approaches to the design and packaging of a high-performance module supporting a 32×32 array of GaAs multiple quantum-well (MQW) modulators flip-chip bonded to a 9×9 mm² complementary metal-oxide-semiconductor (CMOS) chip are described. The module integrates a minilens array, a copper heat spreader, a thermoelectric cooler (TEC) and an aluminum heatsink. The minilens array is aligned and packaged with the chip using a novel six degrees of freedom (DOFs) alignment technique. The kinematic design allows for the manual insertion of the module into a free-space optical system with no need for further adjustments. The chip is mounted directly on a flexible printed circuit board (PCB) using a chip-on-board approach, providing over 200 bond pad connections to the chip. Impedance-controlled lines were operated at 1.0 Gb/s with a crosstalk of 4.0% between nearest neighbor lines. The junction-to-TEC thermal resistance is 0.4°C/W, allowing for the use of a single-stage TEC to regulate the chip at an operating temperature of 40°C under a maximum thermal load of 13.1 W     

A 600-dpi capacitive fingerprint sensor chip and image-synthesistechnique

This paper examines the possibility of a low-cost, high-resolution fingerprint sensor chip. The test chip is composed of 64×256 sensing cells (chip size: 2.7×10.8 mm²). A new detection circuit of charge sharing is proposed, which eliminates the influences of internal parasitic capacitances. Thus, the reduced sensing-capacitor size enables a high resolution of 600 dpi, even using a conventional 0.6 μm CMOS process. The partial fingerprint images captured are synthesized into a full fingerprint image with an image-synthesis algorithm. The problems and possibilities of this image-synthesis technique are also analyzed and discussed     

CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 μm double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 μm×40 μm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications     

A novel semiconductor capacitive sensor for a single-chipfingerprint sensor/identifier LSI

We describe a new semiconductor capacitive sensor structure and the fabrication process for a single-chip fingerprint sensor/identifier LSI in which the sensor is stacked on a 0.5-μm CMOS LSI. To ascertain the influence of the fabrication process and normal usage on the underlying LSI, sensor chips were subjected to an electrostatic discharge (ESD) test, mechanical stress test, and unsaturated pressure cooker test (USPCT). ESD tolerance is obtained at the value of ±3.0 kV. To investigate mechanical stress, we carried out a tapping test. The sensor is immune to mechanical stress under the condition of 10⁴ taps with the strength of 1 MPa. A multilayer passivation film consisting SiN under polyimide film provides protection against contamination such as water. Thus, under USPCT conditions of 130°C, 80% humidity, and 48 h, the chips were not degraded. The tests confirm that the proposed sensor has sufficient reliability for normal identification usage     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

A log-polar image sensor fabricated in a standard 1.2-μm ASICCMOS process

A CMOS log-polar or foveated image sensor for use in mobile robotic and machine vision applications has been designed, fabricated, and tested. The sensor benefits from a high degree of integration, minimal power consumption, and ease of manufacture due to the use of a standard 1.2 μm ASIC CMOS process. The sensor is composed of two distinct CMOS imager arrays which together solve the problem of obtaining good image resolution over a wide field of view. With resolution sensing is accomplished with a 40×40 array of individual pixels each measuring 9.6 μm on a side. A wide field of view is provided by an array of 64×16 pixels arranged on a log-polar grid. The maximum measured dynamic range for the fabricated log-polar array is 46 dB, while the lowest observed fixed-pattern noise is 0.5% of saturation. Combined power consumption of both arrays is under 2 mW when operating from a single 5-V supply at a frame rate of 30 frames/s     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

基于FPGA的大面阵CMOS相机高速率电子学系统设计

目前深空遥感探测多采用CCD作为高分辨率相机的传感器,相较于CCD,面阵CMOS驱动更简单、功耗更低、抗辐射能力更强,是深空遥感探测目前的发展趋势。为此,本文基于CMOSIS公司生产的型号为CMV20000,图像分辨率为5 120×3 840的CMOS探测器,设计完成了一个大面阵CMOS高分辨率相机,图像分辨率为5 120×3 840。详细阐述了以FPGA为核心的电子学系统的整体结构,结合CMV20000的工作模式和时序电路,实现了高分辨图像的高速传输以及数据校正。试验结果表明,设计的相机系统方案合理,解决了CMV20000数据无法对齐的数据校正问题,系统运行稳定可靠,安装光学系统后能够获取高质量图像。     

A high-packing density pixel with punchthrough read-out method foran HDTV interline CCD

A new pixel structure for a high-packing-density interline CCD is proposed, in which signal charges are read out from the photodiodes to the vertical CCD by a punchthrough mechanism. This read-out method makes it possible to reduce the depth of the VCCD channel and the second p-well by implanting these two layers after diffusion of the photodiode n layer. Spreading resistance measurements on dummy wafers show that the depths of these layers are 0.28 μm and 0.6 μm, respectively. Moreover, the photodiode n-layer is covered with a surface p⁺-layer, even at the transfer region. We describe the results of simulations and experiments on a test image sensor with pixel dimensions of 7.3 μm (H)×7.6 μm (V). From the experimental data, we estimate the characteristics of an image sensor with pixel dimension 5.0 μm (H)×5.2 μm (V). Such a device should have a maximum charge handling capability of 1.4×10⁵ electrons, a smear level of -88 dB, a sensitivity of 1.5×10³ electrons/Ix with a 30% fill factor, no image lag, and a low photodiode dark signal of less than 14 electrons at 60°C. These results indicate that an IL-CCD with a punchthrough readout structure is suitable for image sensors with a high pixel density such as 2/3 inch 2 million pixel image sensors for high-definition TV applications     

Random addressable 2048×2048 active pixel image sensor

In this paper, we discuss the design, design issues, fabrication, and performance of a 2048×2048 active pixel image sensor in a 0.5-μm standard CMOS process. Each pixel, 7.5×7.5 μm² , consists of three transistors and a photo diode, resulting in a 12-million transistor chip with a die size of 16.3×16.5 mm. The pixel has a nonintegrating direct readout architecture, with a logarithmic light-to-voltage conversion. This allows the array to be fully random accessible, both in space and time. The sensor has eight analog outputs, each with a pixel rate of 4.5 MHz, which implies a maximum frame rate of eight full frames per second. Sub-sampling or windowing makes higher frame rates possible. The yield of the sensor is high if one accepts a small number of bad pixels     

A 256×256 pixel smart CMOS image sensor for line-based stereovision applications

This paper presents a 256×256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-μm CMOS process with double poly and double metal, giving a pixel pitch of 20 μm and die size of 7×7 mm². A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V     

基于S3C2440的实时捕捉监控系统设计

设计了一款基于S3C2440芯片的最小化实时捕捉监控系统。该系统选择红外传感器、CMOS图像传感器OV9650、TQ043TSCM-V型LCD、SANDISK的SDHC,分别作为检测模块、图像采集模块、实时显示模块和储存模块。为使监控系统具有良好的实时性以及小巧的程序代码,采用裸机编程。经实际验证,系统对物体捕捉敏感,图像显示连续清晰,体现了良好的稳定性,具有较好的应用价值。     

Reset noise reduction through column-level feedback reset in CMOS image sensors

A low reset noise CMOS image sensor(CIS) based on column-level feedback reset is proposed.A feedback loop was formed through an amplifier and a switch.A prototype CMOS image sensor was developed with a 0.18μm CIS process.Through matching the noise bandwidth and the bandwidth of the amplifier,with the falling time period of the reset impulse 6μs,experimental results show the reset noise level can experience up to 25 dB reduction.The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems,especially in low illumination.