W‐Band MMIC chipset in 0.1‐μm mHEMT technology

We developed a 0.1‐μm metamorphic high electron mobility transistor and fabricated a W‐band monolithic microwave integrated circuit chipset with our in‐house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz–108 GHz band and achieved excellent spurious suppression. A low‐noise amplifier (LNA) with a four‐stage single‐ended architecture using a common‐source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W‐band image‐rejection mixer (IRM) with an external off‐chip coupler was also designed. The IRM provided a conversion gain of 13 dB–17 dB for RF frequencies of 80 GHz–110 GHz and image‐rejection ratios of 17 dB–19 dB for RF frequencies of 93 GHz–100 GHz.     

A New Approach for Built‐in Self‐Test of 4.5 to 5.5 GHz Low‐Noise Amplifiers

This paper presents a low‐cost RF parameter estimation technique using a new RF built‐in self‐test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.     

Low-cost test technique using a new RF BIST circuit for 4.5-5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.     

E‐Band Wideband MMIC Receiver Using 0.1 µm GaAs pHEMT Process

In this paper, the implementations of a 0.1 µm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single‐chip receiver for 70/80 GHz point‐to‐point communications are presented. To obtain high‐gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five‐stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five‐stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of –1.5 dBm to 1.5 dBm. Finally, a single‐chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of –21 dBm.     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。     

A Novel RF Test Scheme Based on a DFT Method

This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides the input impedance, gain, noise figure, voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by utilizing the output DC voltages from the DFT chip. This technique can save marginally failing chips in production testing as well as in the system, hence saving a tremendous amount of revenue from unnecessary device replacements.     

一款130～140GHz MMIC低噪声放大器

基于90 nm栅长的InP高电子迁移率晶体管(HEMT)工艺,研制了一款工作于130 ～140 GHz的MMIC低噪声放大器(LNA).该款放大器采用三级级联的双电源拓扑结构,第一级电路在确保较低的输入回波损耗的同时优化了放大器的噪声,后两级则采用最大增益的匹配方式,保证了放大器具有良好的增益平坦度和较小的输出回波损耗.在片测试结果表明,在栅、漏极偏置电压分别为-0.25 V和3V的工作条件下,该放大器在130～ 140 GHz工作频带内噪声系数小于6.5 dB,增益为18 dB±1.5 dB,输入电压驻波比小于2:1,输出电压驻波比小于3:1.芯片面积为1.70 mm×1.10 mm.该低噪声放大器有望应用于D波段的收发系统中.     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

采用电流复用拓扑的宽带收发一体多功能电路

基于标准的GaAs赝配高电子迁移率晶体管(PHEMT)单片微波集成电路(MMIC)工艺设计并制备了一款宽带收发一体多功能电路芯片.该多功能芯片包含了功率放大器、低噪声放大器和收发开关.放大器采用电流复用拓扑结构实现了低功耗的目标.收发开关采用浮地结构避免了使用负电源.芯片在14～ 24 GHz工作频率的实测结果显示:接收支路噪声系数小于3.0dB,增益大于18 dB,输入及输出电压驻波比(VSWR)均小于2.0,1 dB压缩点输出功率大于0 dBm,直流功耗为60 mW;发射支路增益大于21 dB,输入输出VSWR均小于1.8,1dB压缩点输出功率大于10 dBm,直流功耗为180 mW.芯片尺寸为2 600 μm×1 800 μm.该多功能收发电路的在片测试结果和仿真结果一致,性能达到了设计要求.     

DC-20 GHz CMOS LNA using novel multilayered transmission lines and inductors

A distributed low-noise amplifier (LNA) employing novel multilayered transmission lines and inductors is designed in a standard 0.18 mum CMOS process. The new LNA provides significant improvement in performance and size with less than 13 dB return loss from DC to 17 GHz, average gain of 8plusmn0.2 dB from DC to 20 GHz, noise figure of 3.4-5 dB from 0.5-19 GHz, power consumption of 34.2 mW, and 1.05times0.37 mm ² chip size including RF pads     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

超低功耗Q波段低噪声放大器芯片的设计和实现

采用GaAs赝配HEMT单片微波集成电路(MMIC)工艺和堆栈偏置技术设计实现了一款Q波段低噪声放大器(LNA)芯片.该放大器采用4级级联的堆栈偏置拓扑结构,前两级电路在确保较低输入回波损耗的同时优化了放大器的噪声系数,后两级电路则采用最大增益的匹配方式,确保放大器具有良好的增益平坦度和较小的输出回波损耗.该LNA芯片最终尺寸为3 250 μm×1 500 μm,实测结果表明在40～46 GHz工作频率内放大器工作稳定,小信号增益大于23 dB,噪声系数小于3.0 dB,在4.5V工作电压下消耗电流约6 mA.此外,在片实测结果和设计结果符合良好.     

A 50‐mA 1‐nF Low‐Voltage Low‐Dropout Voltage Regulator for SoC Applications

In this paper, we present a low‐voltage low‐dropout voltage regulator (LDO) for a system‐on‐chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1‐nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop‐out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

A Ka-band low-noise amplifier with a coplanar waveguide (CPW) structure with 0.15-μm GaAs pHEMT technology

This investigation explores a low-noise amplifier (LNA) with a coplanar waveguide (CPW) structure, in which a two-stage amplifier is associated with a cascade schematic circuit, implemented in 0.15-μm GaAs pseudo-morphic high electron mobility transistor (pHEMT) technology in a Ka-band (26.5-40.0 GHz) microwave monolithic integrated circuit (MMIC). The experimental results demonstrate that the proposed LNA has a peak gain of 12.53 dB at 30 GHz and a minimum noise figure of 3.3 dB at 29.5 GHz, when biased at a V_(ds) of 2 V and a V_(gs) of-0.6 V with a drain current of 16 mA in the circuit. The results show that the millimeter-wave LNA with coplanar waveguide structure has a higher gain and wider bandwidth than a conventional circuit. Finally, the overall LNA characterization exhibits high gain and low noise, indicating that the LNA has a compact circuit and favorable RF characteristics. The strong RF character exhibited by the LNA circuit can be used in millimeter-wave circuit applications.     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

High Performance Millimeter‐Wave Image Reject Low‐Noise Amplifier Using Inter‐stage Tunable Resonators

A Q‐band pHEMT image‐rejection low‐noise amplifier (IR‐LNA) is presented using inter‐stage tunable resonators. The inter‐stage L‐C resonators can maximize an image rejection by functioning as inter‐stage matching circuits at an operating frequency (F_OP) and short circuits at an image frequency (F_IM). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L‐C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR‐LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and F_IM/F_OP of the reported millimeter/quasi‐millimeter wave IR‐LNAs.     

宽带高增益输出平衡CMOS低噪声放大器的设计

设计了一种带片内变压器、适用于0.05～2.5 GHz频段的宽带低噪声放大器(LNA).电路设计采用了并行的共栅共源放大结构,将从天线接收到的单端输入信号转换为一对差分信号输出给后级链路.针对变压器结构的LNA噪声系数不够低和输出不平衡的问题,采用了缩放技术、噪声消除技术以及两级的全差分放大器作为输出缓冲级,来有效降低电路的噪声系数,提高增益和输出平衡度.电路采用TSMC 0.18μm 1P6M RF CMOS工艺设计仿真和流片,测试结果表明:在0.05 ～ 2.5 GHz频带范围内,该LNA的最高功率增益达24.5 dB,全频段内噪声系数为2.6～4 dB,输入反射系数小于-10 dB,输出差分信号幅度和相位差分别低于0.6dB和1.8°.     

0.2μm GaAs PHEMT3.1~10.6GHz宽带低噪声放大器设计

采用OMMIC公司提供的0.2μm GaAs PHEMT工艺(fT=60 GHz)设计并实现了一种适用于宽带无线通信系统接收前端的低噪声放大器。在3.1~10.6 GHz的频带内测试结果如下:最高增益为13 dB;增益波动<2dB;输入回波损耗S11<-11 dB;输出回波损耗S22<-16 dB;噪声系数NF<3.9 dB。5 V电源供电,功耗为120mW。芯片面积为0.5 mm×0.9 mm。与近期公开发表的宽带低噪声放大器测试结果相比较,本电路结构具有芯片面积小、工作带宽大、噪声系数低的优点。